ASIC Verification Engineer

Broadcom; Bengaluru; Hybrid; INR 2,400,000 - 4,200,000; Full time

Job summary

Broadcom in Bengaluru, India is seeking an ASIC Verification Engineer with 8+ years experience to join a team working on AI Network Infrastructure ecosystems. You will develop and maintain verification environments in SV/UVM and collaborate with Arch/uArch/Design for test plan development.

The role requires expertise in SystemVerilog/UVM, co-simulations HW/SW, and experience with VCS/Verdi/Jasper; familiarity with PCIe, Ethernet, AXI4.0, JTAG/I2C, and coverage-driven methodology.

Qualifications

• 8+ years of verification experience.
• Wide exposure to chip-level (SoC) verification.
• Solid SystemVerilog/UVM experience.
• Scripting exposure: Perl or Python or SED/Awk.

Responsibilities

• Develop and maintain verification environments in SV/UVM.
• Collaborate with Arch/uArch/Design to develop and close feature sets across blocks/top level.
• Perform coverage closures and gate-level simulations along with end-to-end verification.
• Engage in test plan development and HW/SW co-simulation debugging.

Skills

SystemVerilog/UVM

HW/SW co-simulation

Perl/Python

JTAG/I2C/PLLs

PCIe/Ethernet/AXI4.0

VCS/Verdi/Jasper

Emulation/Proof tools

Networking protocols L2-L4

Education

Bachelor's/Master's/PhD in a related field

SoC verification exposure

Tools

VCS

Verdi

Jasper

Emulation platforms

Job description

ASIC VERIFICATION ENGINEER

What You can Expect

• Work on Latest cutting edge CSG Switches.
• To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem.
• Develop and maintain verification Environment in Mix of SV/UVM.
• Understanding of the End to End spec along with Network & System topology.
• Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level.
• Coverage Closures, Gate Level Simulations along with end to end verification cycle.

What we are looking for

• Bachelor's/Masters/PhD with Verification experience of 8+ years
• Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST
• Exposure to any one of the scripting languages - Perl or Python or SED/Awk
• Expertise in Co-Simulations (HW/SW) Flow and debugs
• Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary.
• Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0
• Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc
• Experience in GLS, Coverage Driven Methodology, ATE
• Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper.
• Exposure to Test Bench Accelerators /Emulation Platforms.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

Experience Level Senior Level