Manager, ASIC DV

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Hyderabad is looking for an experienced verification engineer with at least 14 years of domain expertise. The role emphasizes managing IP/SS verification utilizing SV/UVM methodologies while ensuring high quality and efficiency.

You will interact closely with architecture and design teams, lead team deliverables, and innovate methodologies to improve automation. Ideal candidates have a robust background in PCIe protocols and a solid understanding of storage architectures.

Qualifications

• 14+ years of overall verification domain experience.
• 12+ years of experience in IP/SS verification using SV and UVM.
• 3+ years of experience managing teams of 10+ engineers.

Responsibilities

• Verification of high-speed IPs using best methodologies.
• Lead deliverables for IP/SS verification using SV/UVM.
• Plan and strategize team execution for verification environments.

Skills

IP/SS verification

SV/UVM methodologies

PCIe protocols

Team management

Automation

Education

Bachelor’s or Master’s in Engineering

Job description

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Responsibilities

• Verification of high‑speed IPs like PCIe and subsystems using best‑in‑class methodologies and processes.
• Lead and drive deliverables for IP/SS verification using SV/UVM‑based verification.
• Planning and strategizing team execution towards efficient, scalable IP/SS verification environments and methodologies.
• Interact with architecture and design teams to establish standard flows and deliverables alignments.
• Understand architecture requirements and support through end‑product quality assurance.
• Work across a challenging schedule and maximize team efficiency using automation, portability, and reusability.
• Lead and drive silicon bring‑up.
• Plan and ramp up the team to enable multiple IP/SS verifications in parallel with high quality and efficiency.

Job Qualifications

• Bachelor’s or Master’s in Engineering with overall verification domain experience of 14+ years.
• Minimum 12+ years of experience in IP/SS verification using SV and UVM.
• Expert level experience on PCIe protocols (Root‑Complex, Endpoints and SR‑IOV).
• Minimum 3+ years of experience managing teams of 10+ engineers and leads.
• Experience collaborating with engineering teams across multiple geographies.
• Strong understanding of storage controller architectures, processor architecture and SOC verification methodologies.
• Knowledge of industry‑standard interfaces such as PCIE‑NVME, NAND and AXI is an advantage.
• Ability to improvise methodologies and drive automation toward efficient execution.
• Experience in career planning, technical mentoring and coaching of junior engineers.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.