Staff engineer , ASIC AMS Verification

1840 Micron Tech. OP India LLP; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP is seeking a highly skilled Engineer for their high-speed DDR and ONFI PHY design team in Bengaluru, India. The candidate will work on designing scalable verification environments using SystemVerilog/UVM and authoring behavioral models to enhance chip-level verification efficiency.

The ideal applicant should have over 5 years of experience, expertise in analog circuit modeling, and a solid understanding of relevant protocols. This role also involves mentoring junior team members and collaborating closely with other designers in the team.

Qualifications

• 5+ years of experience in high-speed DDR and ONFI PHY design.
• Strong background in UVM and AMS simulations.
• Proficient in Verilog and SystemVerilog languages.

Responsibilities

• Part of a challenging high-speed design team.
• Design metric-driven verification environments using SystemVerilog/UVM.
• Author behavioral models and support full-chip co-simulation.

Skills

Logic simulation

UVM environment

AMS simulations

Analog blocks understanding

RTL debugging

NAND ONFI and DFI protocols understanding

Verilog and SystemVerilog

Modelling complex analog circuits

Education

M.S./M.Tech, BS/BE (Electronics)

Job description

Job Description

To be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodes. UVM-AMS Integration: Design scalable, reusable metric-driven verification environments using SystemVerilog/UVM combined with mixed-signal simulators. Real Number Modeling (RNM): Author precise and fast behavioral models using SystemVerilog (EEnet/wreal) or Verilog-AMS to replace heavy SPICE sub‑circuits, drastically accelerating chip‑level verification. Full‑Chip Co‑Simulation: Bring up and support top‑level gate‑level simulations (GLS), power‑aware verification (UPF/CPF), and mixed‑signal co‑simulations to catch interface bugs. Responsible for overall IP and sub‑system verification from test plan creation, UVM development to signoff. Leading, mentoring and coaching junior team members. Work closely with Digital and Analog designers.

Skills Required

• Good experience of logic simulation, UVM environment and testbench creation
• Experience in AMS simulations
• Understanding of Analog blocks like SDLL, DCC, Band gap
• Experience with RTL debugging, scoreboarding, and code coverage analysis
• Understanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocols
• Sound knowledge of Verilog and SystemVerilog languages
• Exposure to modelling and validating complex analog circuits in Verilog and Verilog‑A

Qualifications

M.S./M.Tech, BS/BE (Electronics)

Experience Required

5+ Years

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.