AMSV Lead

Cyient; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Cyient, based in Bengaluru, seeks an AMS verification engineer to develop and maintain verification methodologies for mixed-signalSOC/IPs. You will run SPICE and digital simulations, review specifications, and collaborate with analog and digital teams to ensure correct test conditions.

Strong expertise in SystemVerilog, UVM, and analog behavioural modelling, along with hands-on scripting (Python/Perl/TCL) for automation, is required.

Qualifications

• Expert Knowledge of AMS verification methodologies including mixed signal simulation, assertion and checkers-based verification and analog behavioural modelling.
• Advanced proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms.
• Excellent skills in SystemVerilog, UVM and analog behavioural modelling languages (SV-RNM/Verilog-AMS/Verilog-A).

Responsibilities

• Development of AMS simulation methodologies/flows and verification plans.
• Review specifications and develop verification plan; manage BOM and netlist generations.
• Collaborate with analog and digital design teams to track updates and ensure test conditions.
• Run and debug SPICE based and digital simulations for AMS SOC/IPs and subsystems.
• Speed up debug and improve verification turnaround with waveform tools; create regression setups.
• Document verification findings and methodology updates; contribute to team debugging sessions.

Skills

AMS verification

SystemVerilog

UVM

Analog modeling

Digital concepts

SPICE simulations

Python scripting

Perl scripting

TCL scripting

Tools

Cadence Virtuoso

Synopsys VCS

Verilog-AMS

Verilog-A

Xcelium

Cadence

Synopsys

Job description

• Development of AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS).
• Manage and Review specifications, developing verification plan.
  Manage BOM, netlist generations.
• Interacting with cross functional teams (analog design, digital design) to manage and track updates from and analog and RTL.
• Plan work distribution in the team and ownup few of the critical tasks for hands on execution
  Run and debug SPICE based and digital simulations for AMS SOC/IPs and subsystems
  Understand analog and digital design intent, review simulation setups and ensure correct test conditions.
  Analyse results using waveform/debug tools and identify root cause for functional mismatch
• Use simulation and waveform tools to speed up debug and improve verification turnaround time
• Create and manage regression setup
• Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS, and optimize testbenches in tools like Xcelium, Cadence, or Synopsys flows.
• Contribute to improving simulation workflows (run scripts, log parsing, automation, regression)
• Document verification findings, debug notes and simulation methodlogy updates
• Contribute to the overall success of the team by actively participating in debugging sessions, providing valuable insights, supervise, train and maintaining effective communication within the team.

Skills we are looking for:

• Expert Knowledge of AMS verification methodologies including mixed signal simulation, assertion and checkers-based verification and analog behavioural modelling
• Advanced proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms
• Excellent skills in Systemverilog, UVM and analog behivioral modelling languages (SV-RNM/Verilog-AMS/Verilog-A)
• Strong fundamentals of Analog and Digital concepts.
• Hands on experience with SPICE and digital simulation tools and debug environments
• Comfortable working in a collaborative team setup with clear communication
• Employ scripting languages (PERL, TCL, Python) for automation and efficiency in verification processes.