AMS Verification Engineer (BB48FT RM 4317)

Source-Right; Hyderabad; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Source-Right in Hyderabad, India seeks an AMS Verification Engineer to advance analog/mixed-signal verification for complex SoCs and IPs. You will build verification environments, develop RNMs and models, and verify block-level and subsystem-level designs with a focus on first-pass silicon success.

The role requires 4-8 years of AMS verification experience and expertise in SystemVerilog, Verilog-AMS, UVM, and Cadence/Synopsys tools.

Qualifications

• 4-8 years of experience in AMS Verification or related fields.
• Hands-on verification with analog/mixed-signal blocks and models.
• Experience in SystemVerilog, Verilog-AMS and RNM-based verification.

Responsibilities

• Develop and execute verification plans for AMS IPs and SoCs.
• Create and maintain SystemVerilog, Verilog-AMS and RNM models.
• Develop AMS testbenches and verification environments.
• Perform block- and subsystem-level verification of AMS designs.
• Run schematic-vs-model checks and validation.
• Analyze simulations, debug failures and perform root-cause analysis.
• Collaborate with Design, Modeling and Validation teams for closure.
• Develop coverage, assertions and regression suites.
• Automate verification flows with scripting languages.

Skills

AMS Verification

SystemVerilog

Verilog-AMS

UVM

RNM

Xcelium AMS

Spectre

Virtuoso

Python

Waveform analysis

Education

B.E./B.Tech./M.E./M.Tech in Electronics, Electrical, VLSI, ECE or related field

Tools

Cadence Xcelium AMS

Spectre

Virtuoso

SimVision

Synopsys CustomSim

Python

Shell scripting

Job description

Position: AMS Verification Engineer (BB48FT RM 4317)

Job Description

We are seeking a highly motivated AMS Verification Engineer with hands‑on experience in Analog Mixed Signal verification for complex SoC and IP designs. The candidate will be responsible for developing verification environments, creating behavioral models, and validating analog and mixed‑signal blocks to ensure first-pass silicon success.

Position: AMS Verification Engineer (BB48FT RM 4317)

Job Description

We are seeking a highly motivated AMS Verification Engineer with hands‑on experience in Analog Mixed Signal verification for complex SoC and IP designs. The candidate will be responsible for developing verification environments, creating behavioral models, and validating analog and mixed‑signal blocks to ensure first-pass silicon success.

Educational Qualification

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, ECE, or related field.

Experience

4-8 years of experience in AMS Verification, Analog Verification, Mixed Signal Verification, or AMS Modeling

Key Responsibilities

• Develop and execute verification plans for Analog Mixed Signal (AMS) IPs and SoCs.
• Create and maintain SystemVerilog, Verilog-AMS, and Real Number Models (RNM) for mixed‑signal verification.
• Develop AMS testbenches and verification environments.
• Perform block‑level and subsystem‑level verification of analog and mixed‑signal designs.
• Execute schematic‑versus‑model correlation and validation.
• Analyze simulation results, debug failures, and perform root cause analysis.
• Work closely with Design, Modeling, and Validation teams to achieve verification closure.
• Develop functional coverage, assertions, and regression suites.
• Automate verification flows using scripting languages.

Required Skills

• Strong experience in AMS Verification.
• Hands‑on experience with:
• SystemVerilog
• Verilog‑AMS
• UVM
• RNM (Real Number Modeling)
• Experience with Cadence AMS verification flow:
• Xcelium AMS
• Spectre
• Virtuoso
• Good understanding of:
• ADC
• DAC
• PLL
• LDO
• Bandgap References
• PMIC
• Op‑Amps
• Data Converters
• Experience in mixed‑signal co‑simulation and behavioral modeling.
• Strong debugging and waveform analysis skills.
• Knowledge of scripting languages such as Python, Perl, or TCL.

Preferred Skills

• Experience in Power Management verification.
• Knowledge of low‑power verification concepts.
• Exposure to UVM-MS methodology.
• Experience with high‑speed mixed‑signal interfaces.
• Understanding of semiconductor design and verification flows.

Tools

• Cadence Xcelium AMS
• Spectre
• Virtuoso
• SimVision
• Synopsys CustomSim (preferred)
• Python / Shell Scripting