Staff engineer , ASIC AMS Verification

Micron Technology; Bengaluru; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

Micron Technology in Bengaluru is looking for an experienced verification engineer to join their high-speed DDR & ONFI PHY design team. This role involves designing scalable verification environments, ensuring overall IP and sub-system verification, and leading junior team members.

The successful candidate will have at least 5 years of experience, particularly in logic simulation and UVM environments. A strong understanding of Verilog and System Verilog is essential. A supportive work culture and development opportunities are on offer.

Qualifications

• 5+ years of experience in relevant field.
• Ability to design scalable, reusable verification environments.
• Experience in leading and mentoring junior team members.

Responsibilities

• Part of a high-speed DDR & ONFI PHY design team.
• Responsible for overall IP and sub-system verification.
• Work closely with Digital and Analog designers.

Skills

Logic simulation

UVM environment

Testbench creation

AMS simulations

Understanding of Analog blocks

RTL debugging

Scoreboarding

Code coverage analysis

Understanding of DDR/LPDDR JEDEC

Knowledge of Verilog and System Verilog

Modeling complex analog circuits

Education

M.S./M.Tech or BS/BE in Electronics

Job description

Job Description

• To be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodes
• UVM-AMS Integration: Design scalable, reusable metric-driven verification environments using SystemVerilog/UVM combined with mixed-signal simulators. Real Number Modeling (RNM): Author precise and fast behavioral models using SystemVerilog (EEnet/wreal) or Verilog-AMS to replace heavy SPICE sub-circuits, drastically accelerating chip-level verification. Full-Chip Co-Simulation: Bring up and support top-level gate-level simulations (GLS), power-aware verification (UPF/CPF), and mixed-signal co-simulations to catch interface bugs.
• Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
• Leading, mentoring and coaching junior team members
• Work closely with Digital and Analog designers

Skills Required

• Good experience of logic simulation, UVM environment and testbench creation
• Experience in AMS simulations
• Understanding of Analog blocks like SDLL DCC Band gap
• Experience with RTL debugging, score boarding and code coverage analysis
• Understanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocols
• Sound knowledge of Verilog and System Verilog languages
• Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
• M.S./M.Tech, BS/BE (Electronics)

Experience Required

5+ Years

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.