Staff engineer , ASIC AMS Verification

Micron Technology; Hyderabad; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Micron Technology in Hyderabad is looking for a skilled engineer to join their high-speed DDR & ONFI PHY design team. This role involves designing verification environments using SystemVerilog/UVM and mentoring junior team members. Candidates should have over 5 years of experience in logic simulation, AMS simulations, and a strong understanding of DDR/LPDDR protocols.

Applicants with an M.S./M.Tech or BS/BE in Electronics are preferred. Micron is committed to providing equal employment opportunities, ensuring a diverse and inclusive workplace.

Qualifications

• 5+ years of experience in design and verification.
• Good experience of logic simulation and testbench creation.
• Proficient in UVM environment.

Responsibilities

• Design scalable, reusable metric-driven verification environments.
• Author precise and fast behavioral models.
• Lead and mentor junior team members.
• Support top-level gate-level simulations.
• Work closely with Digital and Analog designers.

Skills

Logic simulation

UVM environment

AMS simulations

Understanding of Analog blocks

RTL debugging

Knowledge of DDR/LPDDR JEDEC protocols

Verilog and System Verilog languages

Modelling complex analog circuits

Education

M.S./M.Tech, BS/BE in Electronics

Job description

Job Description

• To be part of a highly skilled and challenging high speed DDR & ONFI PHY design team working on the newest technology nodes
• UVM-AMS Integration: Design scalable, reusable metric-driven verification environments using SystemVerilog/UVM combined with mixed-signal simulators. Real Number Modeling (RNM): Author precise and fast behavioral models using SystemVerilog (EEnet/wreal) or Verilog-AMS to replace heavy SPICE sub-circuits, drastically accelerating chip-level verification. Full-Chip Co-Simulation: Bring up and support top-level gate-level simulations (GLS), power-aware verification (UPF/CPF), and mixed-signal co-simulations to catch interface bugs.
• Responsible for overall IP and sub-system verification from test plan creation, UVM development to signoff.
• Leading, mentoring and coaching junior team members
• Work closely with Digital and Analog designers

Skills Required

• Good experience of logic simulation, UVM environment and testbench creation
• Experience in AMS simulations
• Understanding of Analog blocks like SDLL DCC Band gap
• Experience with RTL debugging, score boarding and code coverage analysis
• Understanding of DDR/LPDDR JEDEC or NAND ONFI and DFI protocols
• Sound knowledge of Verilog and System Verilog languages
• Exposure to modelling and validating complex analog circuits in Verilog and Verilog-A
• M.S./M.Tech, BS/BE (Electronics)

Experience Required

5+ Years

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.