Staff Engineer Analog Mixed signal verification

Infineon Technologies AG; Bengaluru; On-site; INR 2,600,000 - 4,200,000; Full time

Job summary

Infineon Technologies AG in Bengaluru is seeking an AMS Verification Engineer with 5+ years of experience in SystemVerilog RNM, WREAL modeling, and DMS‑based SoC verification. You will develop behavioral models for analog IPs, build verification environments, and implement SVAs to ensure correct power management designs.

You will collaborate with analog designers, drive coverage, and contribute to regression and automation efforts using UVM, scripting, and modern verification flows.

Qualifications

• 5+ years of AMS/Mixed-Signal Verification.
• Proficient in SystemVerilog RNM and WREAL modeling.
• Strong knowledge of UVM and DMS verification.
• Experience with SystemVerilog Assertions (SVA).
• Hands-on: analog IP modeling and verification against schematic simulations.
• SoC-level AMS verification using RNM models and UVM environments.
• Exposure to ADCs, LDOs, Buck/Boost converters, and power switches.
• Scripting skills in Python, Perl, and shell.

Responsibilities

• Develop and maintain SV RNM and WREAL models for analog and mixed-signal IPs.
• Verify and correlate RNM/WREAL models against transistor-level schematics and analog simulation results.
• Develop automated checkers and reusable verification components.
• Create and deploy SystemVerilog Assertions (SVA) to verify protocol, functionality, timing, and design correctness.
• Perform SoC-level analog vector verification using DMS verification flows with UVM testbenches and RNM models.
• Verify AMS IPs such as ADCs, LDOs, Buck/Boost Controllers, Power Switches.
• Analyze simulation results, debug failures, and ensure comprehensive functional coverage.
• Collaborate with analog design teams to establish model-to-schematic correlation.
• Develop automation frameworks and regression infrastructure using scripting languages.
• Contribute to AMS verification methodology enhancements and simulator adoption.

Skills

SystemVerilog RNM

WREAL Modeling

UVM

DMS Verification

SVA

Python

Perl

Shell scripting

AMS/Mixed-Signal Verification

Tools

Cadence Virtuoso

Cadence Xcelium

APS

XPS

AMS/DMS Simulation Environments

Job description

We are looking for a highly motivated AMS Verification Engineer with 5+ years of experience in System Verilog Real Number Modeling (SV RNM), WREAL modeling, Mixed‑Signal Verification, and DMS‑based SoC verification. The candidate will be responsible for developing and validating behavioral models of analog IPs, creating verification environments, implementing SV Assertions, and driving AMS verification for power management and mixed‑signal designs.

Your role Key responsibilities in your new role

• Develop and maintain SV RNM and WREAL models for analog and mixed‑signal IPs.
• Verify and correlate RNM/WREAL models against transistor‑level schematics and analog simulation results.
• Develop automated checkers and reusable verification components.
• Create and deploy System Verilog Assertions (SVA) to verify protocol, functionality, timing, and design correctness.
• Perform SoC‑level analog vector verification using DMS verification flows involving UVM testbenches and RNM models.
• Verify AMS IPs such as:
  • ADCs
  • LDOs
  • Buck/Boost Controllers
  • Multi‑phase Controllers
  • Power Switches
• Analyze simulation results, debug failures, and ensure comprehensive functional coverage.
• Collaborate with analog design teams to establish model‑to‑schematic correlation.
• Develop automation frameworks and regression infrastructure using scripting languages.
• Contribute to AMS verification methodology enhancements and simulator adoption.

Your profile Qualifications and skills to help you succeed

• 5+ years of experience in AMS/Mixed‑Signal Verification.
• Strong expertise in:
  • SystemVerilog RNM (Real Number Modeling)
  • WREAL Modeling
  • UVM Methodology
  • Digital Mixed Signal (DMS) Verification
  • System Verilog Assertions (SVA)
• Hands‑on experience in developing behavioral models for analog IPs and validating them against schematic‑level simulations.
• Experience in SoC‑level AMS verification involving RNM models and UVM environments.
• Strong understanding of analog and mixed‑signal concepts including:
  • Data Converters (ADC)
  • Voltage Regulators (LDO)
  • Power Management ICs
  • Buck/Boost Converters
  • Multi‑phase Controllers
  • Power Switches
• Good understanding of EDA tools and simulators:
  • Cadence Virtuoso Schematic Editor
  • Cadence Xcelium
  • APS (Accelerated Parallel Simulator)
  • XPS
  • AMS/DMS Simulation Environments
• Experience with verification planning, coverage closure, debugging, and regression management.
• Knowledge of assertion‑based verification techniques and methodologies.
• Strong scripting skills in:
  • Python
  • Perl
  • Shell Scripting
• Experience developing verification automation, checkers, and regression flows.

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game‑changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in?

We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.

Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon.

Vidhi Thakkar