Sr Staff Mixed-Signal Verification Engineer

Synopsys, Inc.; Hyderabad; On-site; INR 3,500,000 - 7,000,000; Full time

Benefits offered by this job

Health benefits

Wellness programs

Job summary

Synopsys, Inc. in Hyderabad, India is seeking an experienced AMS verification engineer to own end-to-end sign-off for mixed-signal IP. You will build and maintain UVM/SystemVerilog testbenches and collaborate with analog/digital teams to ensure robust tape-out readiness.

The role requires 8+ years in AMS verification, expertise in Verilog-A/Verilog-AMS, SystemVerilog, UVM, and proficiency with Spectre AMS or Xcelium AMS. You will mentor teammates and drive verification efficiency and quality.

Qualifications

• 8+ years in AMS verification with proven sign-off ownership for mixed-signal designs.
• Expert in SystemVerilog, UVM, testbench architecture and coverage-driven verification.
• Strong knowledge of Verilog-A/Verilog-AMS for behavioral modeling.

Responsibilities

• Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off.
• Build and maintain UVM/systemVerilog environments that integrate Verilog-A/AMS models.
• Debug analog-digital interfaces, convergence issues and cross-domain failures.
• Develop monitors, scoreboards, and automation to catch real bugs.
• Improve AMS simulation efficiency and optimize regression flows.
• Collaborate with analog/digital teams to align verification with design intent.
• Mentor engineers on AMS methodology and best practices.

Skills

SystemVerilog

UVM

Verilog-A

Verilog-AMS

AMS simulators

Python

Constrained-random

Testbench architecture

Tools

Spectre AMS

Xcelium AMS

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the space where analog meets digital, and you know that the hardest bugs live at that boundary. You understand that mixed-signal verification is not just about running simulations, it is about building the methodology that catches the corner case three months before tapeout. You think in test plans, coverage models, and debug strategies that actually close, not just look good in a review.

You are comfortable sitting with an analog designer to understand a bias circuit, then walking back to your desk to model its behavior in Verilog-A and build a UVM environment around it. You do not wait for perfect specs. You ask the right questions, build what you need, and move forward while others are still debating the approach.

You have owned verification sign-off before. You know what it takes to get from 'mostly working' to 'ready to tape out,' and you have the scars to prove it. When a simulation fails at 3am in a regression, you are the one who can read the waveform, trace it back through the analog-digital handshake, and know exactly where to look.

At Synopsys, you will work on complex mixed-signal IP that powers the semiconductor industry. The problems are real, the stakes are high, and what you verify actually ships.

What You'll Be Doing

• Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems across complex IP projects
• Build and maintain UVM/SystemVerilog verification environments that integrate seamlessly with Verilog-A, Verilog-AMS behavioral models, and mixed-signal simulators
• Debug complex analog-digital interface issues, simulation convergence problems, and cross-domain failures using waveform analysis and AMS-specific debug tools
• Develop assertions, monitors, scoreboards, and automated verification infrastructure that catch real bugs, not just check boxes
• Drive AMS simulation efficiency improvements, optimize regression flows, and reduce debug turnaround time across the verification pipeline
• Collaborate daily with analog designers, digital verification engineers, modeling teams, and architecture groups to align verification approach with design intent
• Mentor verification engineers on AMS methodology, review test plans and environments, and drive best practices across the team

The Impact You Will Have

• Your verification methodology will directly determine whether complex mixed-signal IP tapes out on schedule or slips by months
• The coverage models and test scenarios you define will catch silicon bugs before they become expensive respins
• Your automation and regression infrastructure will cut verification cycle time and let the team move faster without sacrificing quality
• The debug frameworks you build will make it possible for junior engineers to solve problems that used to require senior intervention
• Your technical leadership will shape how the team approaches AMS verification on future projects, raising the bar across the organization
• The behavioral models and monitors you create will be reused across multiple IP families, multiplying your impact beyond a single project
• Your collaboration with analog and digital teams will close the gaps that typically cause late-stage integration failures

What You'll Need

• 8+ years of hands-on experience in AMS verification, with a proven track record of owning verification sign-off for mixed-signal designs
• Expert-level proficiency in SystemVerilog and UVM, with deep understanding of testbench architecture, coverage-driven verification, and constrained-random methodologies
• Strong working knowledge of Verilog-A and Verilog-AMS for behavioral modeling and mixed-signal simulation
• Solid understanding of analog circuit behavior, including bias circuits, regulators, PLLs, ADCs, DACs, or other mixed-signal blocks
• Experience with AMS simulators (Spectre AMS, Xcelium AMS, or similar) and waveform debug tools for mixed-signal analysis
• Strong scripting skills in Python, Perl, or Tcl for automation, regression management, and infrastructure development
• Experience with AI/ML-based verification techniques or automation frameworks is a strong plus

Who You Are

• You can walk into a design review, absorb the analog designer's intent, and walk out with a verification plan that actually tests what matters, not just what is easy to code
• You push back when a test plan is too shallow or a coverage model misses a critical corner case, and you do it in a way that moves the conversation forward
• You are the person the team comes to when a regression is failing in a way that makes no sense, because you know how to read a mixed-signal waveform and trace the problem back to its source
• You do not need someone to tell you what to automate, you see the repetitive, error-prone work and you build the tooling to eliminate it
• You mentor by showing, not just telling, you review code, pair on tough debug sessions, and leave people better at their job than they were before
• You are organized enough to manage verification across multiple blocks in parallel and technical enough to dive deep when something does not add up

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.