Staff Engineer - 3DIC

BITSILICA; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

BITSILICA in Bengaluru seeks an experienced ASIC/SoC Physical Design engineer to own the RTL-to-GDSII flow, including floor planning, placement, routing, and CTS. The role covers 3D-IC and signoff execution, with emphasis on low-power design using UPF/CPF and timing closure beyond 1GHz.

The candidate will collaborate with IP and foundry partners, develop automation scripts in TCL, Python, or Perl, and drive tape-outs across advanced nodes (5nm/3nm/2nm). Telemetry and packaging insight are valued.

Qualifications

• Proficient in TCL scripting for automation.
• Strong Python programming for automations and flows.
• Proficient in Perl scripting for legacy flows.

Responsibilities

• Own RTL-to-GDSII flow including physical-aware synthesis, floor planning, placement, routing, and CTS.
• Work on 3D-IC and multi-die assemblies, gap analysis and signoff tasks.
• Focus on low-power implementation using UPF/CPF and tight timing closure for >1GHz designs.
• Collaborate with IP/foundry partners and develop automation scripts in Tcl, Python, or Perl.
• Lead tape-outs and post-layout verification across advanced nodes (5nm, 3nm, 2nm).
• Demonstrate understanding of MMCM, SI, and 3D packaging technologies.
• Utilize industry-standard EDA tools like Cadence or Synopsys for design & signoff.

Skills

Tcl scripting

Python

Perl

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Synopsys ICC2

Synopsys PrimeTime

Job description

• Full-Stack Physical Design: Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
• 3D-IC and Signoff Execution: Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).
• Power & Performance: Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).
• Methodology Development: Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.
• Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).
• Domain Expertise: Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.
• Tool Proficiency: Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).
• Scripting Skills: Proficiency in Tcl (mandatory), Python, or Perl