Senior Staff Verification Engineer For Worldguard

SiFive India Private Limited; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

SiFive India Private Limited is looking for a seasoned verification engineer to join their dynamic team in Bengaluru. The ideal candidate will have over 10 years of experience in design verification, specifically in CPU verification, with a strong command of SystemVerilog and UVM methodology.

This role entails developing scalable verification environments, analyzing architectural specifications, and performing root cause analyses on RTL design issues. A commitment to inclusive excellence is part of our company culture.

Qualifications

• 10+ years of experience in DV, preferably in CPU verification.
• Very good object-oriented programming skills.
• Integration experience with third-party VIPs.

Responsibilities

• Analyze architectural specifications to define verification strategies.
• Design and implement reusable verification environments.
• Perform root cause analysis on RTL design failures.

Skills

SystemVerilog

UVM methodology

Object-oriented programming

Scripting (Python)

Bus interface knowledge (AXI, PCIe)

CPU architecture knowledge (x86, ARM, RISC-V)

Debugging skills

Education

Bachelor’s or Master’s in Engineering

Tools

Verdi

SimVision

Job description

Job Description

• Verification Planning: Analyze architectural specifications to define verification strategies and create comprehensive test plans that outline test cases, checkers, and coverage goals.
• Testbench Development: Design and implement scalable, reusable, and constrained‑random verification environments using SystemVerilog and UVM.
• Stimulus & Constraint Generation: Write complex sequences and constrained‑random tests to stress‑test the IP across corner cases.
• Debugging: Perform deep‑diving root cause analysis on RTL design failures and testbench issues using waveform viewers (e.g., Verdi, SimVision).
• Coverage Closure: Define and track functional and code coverage metrics. Write cover groups and cover points to ensure all architectural features have been exercised.
• Must have knowledge of the RISC‑V and Processor based verification using C.
• Must have knowledge of the security architecture and be fully independent to own and deliver.

Requirements

• 10+ years of experience in DV preferably in CPU verification.
• Bachelor’s or Master’s in Engineering.
• Proficiency in SystemVerilog and UVM methodology.
• Very good object‑oriented programming skills.
• Any CPU architecture knowledge (x86, ARM or RISC‑V) with test writing / test plan implementation experience.
• Any scripting knowledge, preferably Python.
• Bus interface knowledge like AXI or PCIe.
• Integration experience with third‑party VIPs such as bus VIPs.
• CPU micro‑arch knowledge.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India. Any offer of employment for this position is contingent on the Company verifying that you are authorised for access to export‑controlled technology under applicable export control laws or that we can obtain any necessary export licence(s) or other approvals.

SiFive is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.