CPU Design Verification Engineer

SiFive India Private Limited; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Benefits offered by this job

Equal opportunity employer

Inclusive work environment

Job summary

SiFive India Private Limited is seeking a Verification Engineer to lead the verification strategy for major out-of-order CPU core subsystems. You will own the testbench design and execution, ensuring compliance and correctness throughout the development cycle.

The ideal candidate will have a strong background in digital verification, micro-architecture, and experience using System Verilog/UVM. This role offers the chance to mentor junior engineers and contribute to key projects in a collaborative environment.

Qualifications

• 3+ years of experience in digital verification with a focus on CPU or similar architectures.
• Strong understanding of micro-architecture concepts and verification methodologies.
• Experience in defining and maintaining assertion sets.

Responsibilities

• Own the verification strategy for major out-of-order core subsystems.
• Develop and maintain coverage models and sign-off criteria.
• Lead debugging of complex failures across cores and caches.
• Mentor junior DV engineers and provide technical leadership.

Skills

Experience in out-of-order CPU verification

Strong debugging skills

System Verilog/UVM knowledge

Mentorship abilities

Education

Bachelor's or Master's degree in Computer Engineering or related field

Job description

Job Description

As part of complex out‑of‑order (OOO) CPU cores verification, we are looking for the role, where you will own verification strategy, methodology, and execution for major core blocks, drive coverage and sign‑off, and act as a technical leader and mentor within the DV team.

Key Responsibilities

• Own DV for major OOO core subsystems such as:
  • Front‑end: fetch, branch prediction, instruction decode.
  • Rename / register mapping and dependency tracking.
  • Issue queues / schedulers, execution units, bypass networks.
  • Reorder buffer (ROB), retirement, exceptions, interrupts, and pipeline flush/replay.
  • Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences, speculative loads/stores.
  • L1 caches, TLBs, MMU interfaces, and coherence/protocol interfaces.
• Translate ISA + micro‑architecture specifications into detailed verification plans and test strategies.
• Testbench & Methodology Leadership
  • Architect and implement System Verilog/UVM testbenches for OOO cores and subsystems: reusable UVM environments, agents, monitors, scoreboards, reference models.
  • Constrained‑random and targeted stimulus for OOO corner cases (deep speculation, hazard patterns, reorder stress).
  • Define and evolve DV methodology for OOO verification: scenario libraries for speculation, memory ordering, and multi‑core interactions.
  • Reuse patterns across IPs and projects; contribute to common DV infrastructure.
• Coverage, Assertions, and Sign‑off
  • Define coverage models and sign‑off criteria: functional, code, assertion, and scenario coverage for OOO execution and memory model compliance.
  • Develop and maintain assertion sets (SVA) for key OOO properties, such as: no deadlock/livelock in ROB / scheduler / LSQ, correct branch mispredict, exception, and interrupt recovery, correct load‑store ordering, forwarding, and replay behavior.
  • Drive coverage closure and sign‑off for owned blocks; review and sign off plans/coverage for peer areas when needed.
• Debug & Cross‑Functional Collaboration
  • Lead debug of complex failures: subtle OOO bugs (hazards, wrong‑path effects, starvation, corner replay conditions), memory ordering and coherence violations across cores and caches, TLB/MMU and privilege/protection corner cases.
  • Work closely with micro‑architecture and RTL teams to refine designs for correctness and verifiability; with performance/modeling teams to align micro‑arch behavior with models and performance targets; with post‑silicon teams to reproduce and root‑cause silicon issues in pre‑silicon DV.
• Mentoring & Influence
  • Mentor junior and mid‑level DV engineers in OOO micro‑architecture concepts and debug, testbench design, stimulus generation, coverage, and methodology.
  • Provide technical leadership across projects: lead DV design and reviews, contribute to architecture/micro‑architecture reviews from a verification perspective.
  • Champion best practices in DV and help set technical direction for core verification.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in: India.

Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.