Staff DFT Engineer

Broadcom; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Broadcom in Bengaluru is seeking an expert DfT engineer to drive test insertion, compression and ATPG verification for mixed-signal IC designs.

You will define DfT strategy, perform gate-level and timing simulations, collaborate with design and layout teams, and support silicon debug with ATE pattern delivery. Proficiency in Primetime, SystemVerilog interfaces and scripting is required.

Qualifications

• Experience in DfT concepts and verification methodologies.
• Hands-on experience with DfT patterns, ATPG coverage and DRC improvements.
• Familiarity with RTL and DfT related scripting.

Responsibilities

• Define DfT Strategy and Requirement Specification for the design
• DfT verification for gate-level and timing simulations
• Work cross sites with design team to define and implement DfT.
• Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.
• Work with STA engineer to define timing constraints for DfT modes. Hands on experience on Primetime will be required.
• Work with Layout engineer to see DFT logic is getting implemented without any issues.
• Support Test engineer in silicon debug and pattern delivery for ATE.
• Experience in RTL coding, shell/Perl scripting.
• Knowledge of System Verilog Interfaces and Lint checks preferred.
• Experienced in handling analog IP DfT simulations.
• Be fluent with all common concepts of DfT and DfT tools.
• R026775

Skills

DfT concepts

ATPG

IJTAG

Memory BIST

JTAG

Mentor DfT tools

Synopsys DC

Primetime

RTL coding

Perl scripting

SystemVerilog interfaces

Lint checks

Analog IP DfT

Tools

Mentor DfT tools

Synopsys DC

Primetime

Job description

Job Description:

• Strong knowledge and experience in Scan Insertion, Compression, ATPG, Memory BIST and JTAG at IC level for mixed signal designs
• Looking for Expert at IJTAG, SSN, ATPG Verification
• Experience in Mentor DfT tools, Synopsys DC and simulator tools.
• Define DfT Strategy and Requirement Specification for the design
• DfT verification for gate-level and timing simulations
• Work cross sites with design team to define and implement DfT.
• Hands on experience in solving DfT problems, simulation failures, ATPG coverage and DRC improvements.
• Work with STA engineer to define timing constraints for DfT modes. Hands on experience on Primetime will be required.
• Work with Layout engineer to see DFT logic is getting implemented without any issues.
• Support Test engineer in silicon debug and pattern delivery for ATE.
• Experience in RTL coding, shell/Perl scripting.
• Knowledge of System Verilog Interfaces and Lint checks preferred.
• Experienced in handling analog IP DfT simulations.
• Be fluent with all common concepts of DfT and DfT tools.
• R026775

Requirements: