Sr. Staff RTL Eng

Lattice Semiconductor; Maharashtra; On-site; INR 4,500,000 - 6,500,000; Full time

Job summary

Lattice Semiconductor in India is seeking a Senior Staff Design Engineer – Machine Learning Engine RTL to drive RTL development for a ML inference engine on low‑power FPGA devices. You will optimize data paths for throughput and latency, design ML operators, and collaborate with algorithm and architecture teams to map models into efficient hardware.

Strong HDL skills and FPGA experience are essential for this role.

Qualifications

• BE/MTech/PhD in Electronics, Electrical or Computer Engineering.
• Minimum 14 years of experience in RTL design (12 years for MTech and 8 years for PhD).
• Independent, self-motivated, capable of executing under dynamic environments and uncertainties.
• Innovative, problem-solver who likes to develop better solutions for existing problems.
• Strong cross-team communication and technical documentation skills.

Responsibilities

• Lead the design and development of RTL for a machine‑learning engine that infers neural networks on resource‑constrained low‑power FPGA devices.
• Optimize data paths for high throughput and low latency, design ML operators efficiently, and collaborate with algorithm and architecture teams to translate ML models and operators into efficient hardware micro‑architectures.
• Take ownership of optimizing machine‑learning pipelines for computer vision, robotics, human‑machine interaction, or other related domains.

Skills

RTL design

Verilog

SystemVerilog

HDL simulation

FPGA/ASIC flow

Convolution

Image processing

Education

BE in Electronics

MTech in ECE

PhD in EE/CE

Job description

Company Overview

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market‑leading intellectual property and low‑power, small‑form‑factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost‑ and power‑efficient products. The company's broad, end‑market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long‑standing relationships and commitment to world‑class support enable our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world. The control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better‑connected. Help us continue to drive innovation that creates a smarter, better‑connected world.

Position Summary

Senior Staff Design Engineer – Machine Learning Engine RTL

Responsibilities

Lead the design and development of RTL for a machine‑learning engine that infers neural networks on resource‑constrained low‑power FPGA devices. Optimize data paths for high throughput and low latency, design ML operators efficiently, and collaborate with algorithm and architecture teams to translate ML models and operators into efficient hardware micro‑architectures. Take ownership of optimizing machine‑learning pipelines for computer vision, robotics, human‑machine interaction, or other related domains.

Key Skills

• In‑depth experience in designing and developing RTL using Verilog and System Verilog‑HDL
• Functional simulation experience with industry standard tools such as Xcelium‑Cadence and VCS‑Synopsys
• Good understanding of machine‑learning operations such as convolution
• Architecture and design of RTL for machine‑learning compute engines targeting low‑power FPGA platforms
• Collaboration with algorithm and architecture teams to translate ML models and operators into efficient hardware micro‑architectures
• Experience in image‑processing and DSP algorithms implementation
• Deep understanding of machine‑learning data models to optimally map them into hardware
• Experience with FPGA/ASIC synthesis flow and timing closure
• Working knowledge of computer architecture and memory management
• Experience with C and/or SystemC (a plus)

Education and Experience

• BE/MTech/PhD in Electronics, Electrical or Computer Engineering
• Minimum of 14 years of experience in RTL design (12 years for MTech and 8 years for PhD)
• Independent, self‑motivated, capable of executing under dynamic environments and uncertainties
• Innovative, problem‑solver who likes to develop better solutions for existing problems
• Strong cross‑team communication and technical documentation skills

Additional Information

This position requires a successful background and reference checks and satisfactory proof of right to work in India. Employees are valued and recognized for their contributions in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees.

EEO & Diversity Statement

At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.