Sr. Staff RTL Eng

Lattice Semiconductor; Pune District; Presencial; INR 2 500 000 - 3 500 000; Tempo integral

Resumo da oferta

A leading technology company in Pune District is seeking a Senior Staff design engineer to design and develop RTL for Machine Learning engines. The ideal candidate will have extensive experience in RTL design, specifically using Verilog and System Verilog-HDL, along with a deep understanding of machine learning and hardware optimization. If you thrive in a collaborative environment and bring innovative solutions, this opportunity is for you.

Qualificações

• 14+ years experience in RTL design (12 for MTech, 8 for PhD).
• Independent and self-motivated in dynamic environments.
• Good cross team communication and technical documentation.

Responsabilidades

• Design and develop RTL for Machine Learning engine.
• Implement ML operators on low power FPGA.
• Optimize data paths for high throughput and low latency.

Conhecimentos

RTL design using Verilog

Functional simulation

Understanding of ML operations

Machine Learning compute engines

Image processing and DSP algorithms

FPGA/ASIC synthesis flow

C and/or SystemC

Formação académica

BE/MTech/PhD in Electronics, Electrical or Computer Engineering

Ferramentas

Xcelium-Cadence

VCS-Synopsys

Descrição da oferta de emprego

Lattice Overview

There is energy here… energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world‑class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results‑oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market‑leading intellectual property and low‑power, small form‑factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products. The Company's broad, end‑market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long‑standing relationships and commitment to world‑class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world.

Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better‑connected. Join Team Lattice…and help us continue to drive innovation that creates a smarter, better‑connected world. Together, we enable what’s next.

sensAI team at Lattice Semiconductor, innovates and creates solutions to enable edgeAI with programmable low power devices. Our vision is to unleash FPGA to add intelligence to every sensor used in Automotive, industrial and consumer products. As a senior member of the team, you will be responsible for developing and enhancing machine learning engine that infers neural networks on resource constrained devices. You need to bring expertise in machine learning to enable computer vision, robotics, human‑machine interaction, or other related domains.

Job Description

We are seeking a highly motivated Senior Staff design engineer who will be responsible for design and development of RTL for Machine Learning engine. You are responsible to implement ML operators efficiently using resources on low power FPGA. You need to bring experience in optimizing data path for high throughput and low latency. Good understanding of neural network accelerators and/or DSP processors is essential to be successful in this job.

Key Skills

• In-depth experience in designing and developing RTL using Verilog, System Verilog‑HDL.
• Ability to carry out functional simulation using industry standard simulation tools such as Xcelium‑Cadence, VCS‑Synopsys.
• Good understanding of ML operations like convolution.
• Architect and design RTL for Machine Learning compute engines targeting low‑power FPGA platforms.
• Collaborate with algorithm and architecture teams to translate ML models/operators into efficient hardware micro‑architectures.
• Experience in image processing and DSP algorithms implementation.
• Deep understanding of machine learning, data models to optimally map it with hardware.
• Experience in FPGA/ASIC synthesis flow, timing closure.
• Working knowledge of computer architecture and memory management.
• Experience with C and/or SystemC is a plus.

Education And General

• BE/MTech/PhD in Electronics, Electrical or Computer Engineering.
• Minimum of 14 years (12 years for MTech and 8 years for PhD) experience in RTL design.
• Independent and self‑motivated, capable of executing under dynamic environment and uncertainties.
• Innovative, problem solver who likes to come up with newer and better solutions for existing problems.
• Good cross team communication and technical documentation desired.