Senior Design Engineer(FPGA RTL)

Lattice Semiconductor; Hyderabad; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Lattice Semiconductor in Hyderabad, India, is seeking a Senior IP Design engineer with extensive hands-on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debugging.

You will contribute to high-speed IO interfaces (PCIe, Ethernet, CPRI, JESD204B/C), pursue hardware validation, and develop soft IP packaging and testbenches in a fast-paced, collaborative environment.

Qualifications

• Hands-on FPGA RTL design, verification, and timing closure.
• Proficient in C/C++, Python, TCL or Perl.
• Experience with high-speed IO protocols (PCIe, Ethernet, CPRI, JESD204B/C).
• Background in hardware validation and debugging is a plus.
• Experience with soft IP packaging and testbench development.

Skills

FPGA RTL design

Logic verification

FPGA timing closure

Programming: C/C++/Python/TCL/Perl

High-speed IO protocols (PCIe,Ethernet

Hardware validation & debugging

Soft IP packaging & testbench

Education

BS/MS/PhD in Electronics or Computer Engineering

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description

We are seeking a Senior IP Design engineer with significant hands‑on experience in FPGA RTL design, logic simulation, FPGA compilation and timing closure and hardware debug.

Requirements

Key Skills

• Hands‑on experience in FPGA RTL design, logic verification, debug and timing closure


• Programming skills (e.g.: C/C++, Perl, TCL or Python)


• Experience in high‑speed IO protocols (e.g.: PCIe, Ethernet, CPRI, JESD204B/C)


• Experience in hardware validation and debug is a plus


• Experience in soft IP packaging, example design and testbench development will be an added advantage

Education And General

• BS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of FPGA system design experience.


• Independent and self‑motivated, capable of executing under dynamic environment and uncertainties

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service‑driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS.

At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.