FW Design Eng 2

LSCC India Pvt Ltd; India; On-site; INR 700,000 - 1,000,000; Full time

Job summary

LSCC India Pvt Ltd is seeking a Design Engineer (RTL) to join their FPGA/ASIC design team. The role involves contributing to the design of high-performance digital IP and subsystems in a dynamic environment.

The ideal candidate will hold a Bachelor’s or Master’s in Electronics/Electrical Engineering and possess strong understanding of digital design fundamentals. This position offers opportunities to work closely with cross-functional teams and develop next-generation programmable logic solutions.

Qualifications

• Bachelor’s or Master’s in Electronics/Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design fundamentals.

Responsibilities

• Contribute to the design and implementation of RTL code for complex digital systems.
• Develop and optimize high-performance, low-power digital logic for FPGA/ASIC platforms.
• Participate in micro-architecture definition and design specifications.
• Perform functional validation, debugging, and root-cause analysis of design issues.

Skills

RTL design using Verilog/SystemVerilog

Digital design concepts (FSMs, pipelining)

EDA tools (simulation, synthesis)

Debugging RTL issues

Timing closure understanding

Education

Bachelor’s or Master’s in Electronics/Electrical Engineering

Tools

Python

TCL

Job description

Overview

Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists partnering with world‑class sales, marketing, and support teams, developing programmable logic solutions that are changing the industry.

Job Description

Lattice Semiconductor is seeking a Design Engineer (RTL) to join our FPGA/ASIC design team focused on next‑generation programmable logic and Edge AI solutions. The selected candidate will contribute to the design and development of high‑performance digital IP and subsystems, and will work with global teams in a dynamic engineering environment.

Roles & Responsibilities

• Contribute to the design and implementation of RTL (Register Transfer Level) code for complex digital systems.
• Develop and optimize high‑performance, low‑power digital logic for FPGA/ASIC platforms.
• Work closely with architecture, verification, physical design, and firmware teams to ensure design quality and functionality.
• Participate in micro‑architecture definition and design specifications.
• Perform functional validation, debugging, and root‑cause analysis of design issues.
• Ensure designs meet timing, power, and area (PPA) goals.
• Support synthesis, STA (Static Timing Analysis), and linting flows.
• Collaborate with global cross‑functional teams across multiple sites.
• Participate in design reviews and code reviews to ensure quality and best practices.
• Document design specifications and methodologies.

Qualifications

• Bachelor’s or Master’s in Electronics/Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of digital design fundamentals.

Required Skills

• Proficiency in RTL design using Verilog/SystemVerilog.
• Strong knowledge of digital design concepts (FSMs, pipelining, clocking, reset, low‑power design).
• Exposure to EDA tools (simulation, synthesis, lint, STA).
• Experience with debugging RTL issues and waveform analysis.
• Understanding of timing closure and design constraints.

Preferred Skills

• Experience with FPGA architectures and design flows.
• Familiarity with protocols/interfaces such as AXI, I2C, SPI, UART, PCIe.
• Knowledge of low‑power design techniques and CDC/RDC concepts.
• Exposure to verification methodologies (UVM/SystemVerilog).
• Basic scripting knowledge (Python/TCL).
• Understanding of CMOS technology and semiconductor fundamentals.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

Applications are welcome from all qualified candidates.