Sr Staff DFT Engineer (AI2508)

SiMa.ai; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

SiMa.ai in Bengaluru (Bangalore) is seeking a Sr Staff DFT Engineer to drive block-level and SOC-level DFT, SCAN, MBIST, and JTAG across pre- and post-silicon stages. The role emphasizes RTL/gate-level simulation, timing constraint development, and automation via TCL/Perl.

The candidate should have 7+ years in VLSI DFT, strong Verilog knowledge, experience with Tetramax/Mentor Tessent, and proficiency in scripting languages.

Qualifications

• BSEE/MSEE or equivalent degree with 7+ years of experience.
• In-depth knowledge of VLSI design and Verilog.
• Experience with DFT execution at block-level and SOC-level in advanced finFET tech.
• Strong knowledge of EDA tools such as Synopsys Tetramax or Mentor Tessent.
• Good problem solving and debugging skills.
• Familiarity with hardware simulation tools like VCS, Verdi.
• Proficiency in scripting languages (C/C++/TCL/Perl/Python).
• Ability to work with cross-functional and cross-site teams and strong communication.

Responsibilities

• Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG.
• Develop and execute test insertion flow for scan, MBIST, JTAG.
• Estimate and achieve targeted test coverage.
• Run RTL and gate-level simulation for all DFT modes.
• Develop and debug timing constraints for all DFT modes.
• Verify test patterns pre-silicon and post-silicon.
• Write scripts in TCL and Perl to automate productivity.

Skills

Verilog

C/C++

Python

TCL

Perl

Education

BSEE/MSEE or equivalent

Tools

Synopsys Tetramax

Mentor Tessent

VCS

Verdi

Job description

Job Title: Sr Staff DFT Engineer

(This position requires a full-time, on-site presence in our Bangalore, India office)

Job ID: AI2508

Job Description

• Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG


• Develop and execute test insertion flow for scan, MBIST, JTAG


• Estimate and achieve targeted test coverage.


• Run RTL and gate-level simulation for all DFT modes.


• Develop and debug timing constraints for all DFT modes.


• Verify test patterns pre-silicon and post-silicon


• Write scripts in TCL and Perl to achieve productivity enhancements through automation.

Key Responsibilities

• Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG


• Develop and execute test insertion flow for scan, MBIST, JTAG


• Estimate and achieve targeted test coverage.


• Run RTL and gate-level simulation for all DFT modes.


• Develop and debug timing constraints for all DFT modes.


• Verify test patterns pre-silicon and post-silicon


• Write scripts in TCL and Perl to achieve productivity enhancements through automation.

Required Background

• BSEE/MSEE or equivalent degree with 7+ years of experience.


• In-depth knowledge of VLSI design as well as hardware description languages such as Verilog.


• Experience with complex block-level and SOC-level DFT execution in advanced finFET technology.


• Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.


• Good problem solving and debug capabilities is a preferred plus.


• Good knowledge of hardware simulation tools like VCS, Verdi, etc.


• Proficient in scripting languages (C/C++/TCL/Perl/Python)


• Should be proficient at working with cross functional and cross site teams.


• Must possess good communication skills, be a self-driven individual and a good team player.

Personal Attributes

Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.