Senior DFT Engineer

Recrew AI; Bengaluru Urban; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Recrew AI in Bengaluru is seeking an experienced Design for Test (DFT) engineer to own the full DFT flow for SoC/ASIC designs, from scan insertion to post-silicon bring-up. You will collaborate with design, verification, and physical design teams to accelerate client time-to-market.

The role demands 7+ years in DFT with ATPG, MBIST, JTAG 1149.1, GLS debugging, and memory repair. You will define test architectures, validate patterns, drive DRC checks, and create reference flows and documentation.

Qualifications

• 7+ years of hands-on DFT experience on SoC/ASIC designs.
• Expertise in scan insertion and scan chain stitching.
• Experience with ATPG patterns (stuck-at, transition, bridge, path delay).
• MBIST and memory repair implementation and verification.
• Proficient in DFT rule checks and violation debugging.
• Experience with JTAG/boundary scan (IEEE 1149.1).
• GLS for DFT pattern validation.

Responsibilities

• Define and implement DFT architecture for SoC/ASIC designs, including scan insertion and scan chain stitching
• Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay fault models
• Implement and verify MBIST and memory repair solutions
• Perform DFT rule checks (DRC) and drive resolution of violations
• Support JTAG/boundary scan (IEEE 1149.1) implementation and verification
• Run and debug Gate Level Simulations (GLS) for DFT pattern validation
• Analyse and improve test coverage, pattern count, and test time; support post-silicon bring-up and failure analysis
• Create and maintain DFT documentation, methodology guides, and best-practice flows

Skills

DFT

ATPG patterns

Scan insertion

JTAG boundary scan

GLS debugging

MBIST

Memory repair

Tools

EDA tools

GLS tools

Boundary scan tools

Job description

Function: Design for Test (DFT) / Semiconductor Engineering

Type: Full-time

Industry: Semiconductors, Information Technology & Services

About Company

A Bangalore-based technology consulting firm specialising in Semiconductor ASIC Design Services and Embedded Software Development. Founded by industry veterans with over 100 years of combined semiconductor experience.

The company guides projects from initial specifications all the way to first-pass silicon success. It operates across six verticals: Design & Verification, Physical Design & SignOff, DFT, FPGA Design, Analog & Analog Layout, and Embedded Software.

A close-knit team of 67, with deep multi-foundry capabilities and advanced node expertise from 180nm to 3nm.

Position Overview

This role sits at the heart of the company's DFT vertical, responsible for defining and implementing test architectures that ensure high fault coverage across complex SoC and ASIC designs. The engineer will own the full DFT flow — from scan insertion and ATPG pattern development through GLS debug and post-silicon bring-up support — working across design, verification, and physical design teams to accelerate client time-to-market.

Role & Responsibilities

• Define and implement DFT architecture for SoC/ASIC designs, including scan insertion and scan chain stitching
• Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay fault models
• Implement and verify MBIST and memory repair solutions
• Perform DFT rule checks (DRC) and drive resolution of violations
• Support JTAG/boundary scan (IEEE 1149.1) implementation and verification
• Run and debug Gate Level Simulations (GLS) for DFT pattern validation
• Analyse and improve test coverage, pattern count, and test time; support post-silicon bring-up and failure analysis
• Create and maintain DFT documentation, methodology guides, and best-practice flows

Must Have Criteria

• 7+ years of hands-on DFT experience on SoC/ASIC designs
• Proven experience with scan insertion, scan chain stitching, and ATPG pattern generation (stuck-at, transition, bridge, path delay)
• Experience implementing and verifying MBIST and memory repair solutions
• Proficiency in DFT rule checks (DRC) and violation debug
• Experience with JTAG/boundary scan and IEEE 1149.1 implementation
• Hands-on experience running and debugging Gate Level Simulations (GLS) for DFT patterns
• Exposure to advanced process nodes and industry-standard EDA tools for DFT

Nice to Have

• Experience with post-silicon bring-up and silicon failure analysis
• Familiarity with multi-foundry design environments
• Exposure to advanced nodes (7nm and below)
• Experience authoring DFT methodology documentation and best-practice flows

What We Offer

• Opportunity to work on complex SoC/ASIC projects spanning 180nm to 3nm process nodes
• Close collaboration with industry veterans carrying 100+ years of combined semiconductor expertise
• Skill development through diverse, client-driven semiconductor engagements
• Stable, engineering-first culture in a focused 67-person firm