Sr. SoC Design Verification Engineer

Altera; Bengaluru; On-site; INR 2,385,496 - 3,816,794; Full time

Job summary

Altera is seeking a Sr. SoC Design Verification Engineer in Bengaluru, Karnataka. The role involves pre-silicon system verification and the creation of test cases and test benches using UVM methodology. Candidates should have over 10 years of experience in complex ASIC designs, and familiarity with System Verilog and UVM is essential.

The ideal candidate will also work in a collaborative environment and may have experience with Design for Debug architecture.

Qualifications

• 10+ years of experience with complex ASIC designs and/or verification.
• Familiar with System Verilog language.
• Experience on UVM verification methodology and formal verification method.
• Working knowledge of scripting in Linux/Unix environments.
• Experience with Design for Debug architecture and verification.
• Experience with ARM and RISC Debug Architectures is desired.

Responsibilities

• Pre-silicon system verification including SoC and FPGA.
• Create test cases and test benches using UVM methodology.
• Define verification strategies and plans for effective verification.
• Coordinate cross-functional efforts for full coverage verification.
• Experience on Emulation will be an add-on.

Skills

UVM methodology

System Verilog

Perl or Python scripting

Debug architecture

Strong communication skills

Job description

Job Description

As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.

Responsibilities

• Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
• Create testcase and testbench with UVM methodology
• Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
• Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
• Experience on Emulation will be an add on.

Qualifications

• 10+ years of experience with complex ASIC designs and/or verification
• Familiar with System Verilog language
• Experience on UVM verification methodology, and formal verification method
• Working knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
• Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
• Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
• Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
• Strong communication skills and the ability to work with a team spread across different geography sites
• Flexible in dynamic environment

Job Type

Regular

Shift

Shift 1 (India)

Location

Bengaluru, Karnataka, India

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.