Senior SoC Design Verification Engineer

844 Altera Semiconductor Technology India Pvt. Ltd.; Madhapur; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. seeks a Sr. SoC Design Verification Engineer responsible for design-for-debug architecture verification and creating test cases using the UVM methodology. You will coordinate cross-functional efforts to achieve effective full-coverage verification and use system-level applications to identify performance shortcomings.

Qualified candidates should have over 10 years of experience with ASIC designs, proficiency in SystemVerilog, and strong communication skills. This regular role is based in Madhapur, India, within a dynamic environment.

Qualifications

• 10+ years of experience with complex ASIC designs and/or verification.
• Strong communication skills and ability to work with a geographically distributed team.
• Flexible in a dynamic environment.

Responsibilities

• Pre-silicon system verification covering SoC, FPGA, and Full Chip design verification.
• Create test cases and test benches using UVM methodology for full-chip/system functional verification.
• Define verification strategies, methodology, and test plans to enable effective verification.
• Coordinate/interface cross-functional efforts with Design, SW, and Architecture teams to achieve full coverage verification.

Skills

SystemVerilog

UVM verification methodology

Scripting in Linux/Unix

Perl or Python

Design-for-debug architecture

ARM and RISC debug architectures

Job description

Job Overview

As a Sr. SoC Design Verification Engineer, you will be responsible for design‑for‑debug architecture verification, including creating test cases and test benches using the UVM methodology. The role may involve full‑chip and/or system functional verification, defining verification strategies, methodology, and test plans to enable effective verification. You will coordinate cross‑functional efforts with Design, SW, Architecture teams to achieve a full‑coverage verification plan and use system‑level applications to verify performance and identify shortcomings.

Responsibilities

• Pre‑silicon system verification covering SoC, FPGA, and Full Chip design verification.
• Create test cases and test benches using UVM methodology for full‑chip/system functional verification.
• Define verification strategies, methodology, and test plans to enable effective verification.
• Coordinate/interface cross‑functional efforts with Design, SW, and Architecture teams to achieve full coverage verification.
• Use emulation (if available) to support verification.
• Verify design‑for‑debug architectures, including JTAG, high‑speed USB, PCIe‑based debug, and visualization of internal signals.
• Focus on ARM and RISC debug architectures and engage with UltraSoC/Tessent Embedded Analytics debug architecture as required.

Qualifications

• 10+ years of experience with complex ASIC designs and/or verification.
• Proficiency in SystemVerilog.
• Experience with UVM verification methodology and formal verification methods.
• Working knowledge of scripting in Linux/Unix environments and proficiency in Perl or Python.
• Experience with design‑for‑debug (JTAG, high‑speed USB, PCIe based debug, visualization of internal signals).
• Experience with ARM and RISC debug architectures.
• Experience with UltraSoC/Tessent Embedded Analytics debug architecture is a plus.
• Strong communication skills and ability to work with a geographically distributed team.
• Flexible in a dynamic environment.

Job Details

Job Type: Regular
Shift: Shift1 (India)
Primary Location: Regus, Madhapur
Additional Locations: Posting Statement

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.