Design Verification Engineer

844 Altera Semiconductor Technology India Pvt. Ltd.; New Delhi; Hybrid; INR 800,000 - 1,200,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. is searching for a Design Verification Engineer to drive the design, development, and validation of software frameworks for FPGA acceleration. You will work closely with architects and engineers to create comprehensive verification strategies and develop robust verification environments using SystemVerilog and UVM.

The ideal candidate should have a Bachelor's or Master's degree in Electrical or Computer Engineering and over 3 years of relevant experience in ASIC or FPGA verification. Strong scripting skills in Python or Perl are also essential. Join us and enhance our verification flows!

Qualifications

• 3+ years of experience in ASIC or FPGA design verification.
• Strong hands-on experience in developing UVM-based testbenches and verification components.
• Excellent analytical, problem-solving, and debugging skills.

Responsibilities

• Collaborate with architects and design engineers to define verification strategies.
• Develop robust, reusable, and constrained-random verification environments.
• Execute simulation regressions, debug test failures, and analyze root causes.

Skills

Hardware Description Languages (HDL) such as Verilog or VHDL

SystemVerilog

UVM (Universal Verification Methodology)

Python

Perl

Automation and data analysis

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Simulation and debug tools

Job description

Job Overview

Altera is looking for a talented and driven Design Verification Engineer to design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Key Responsibilities

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained‑random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
• Develop verification components, including drivers, monitors, scoreboards, and checkers.
• Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
• Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
• Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
• Develop automation scripts and infrastructure using languages such as Python or Perl to improve verification efficiency and flows.
• Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in ASIC or FPGA design verification.
• Expertise in Hardware Description Languages (HDL) such as Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
• Strong hands‑on experience in developing UVM‑based testbenches and verification components.
• Proficiency in modern verification methodologies, including coverage‑driven verification (CDV) and assertion‑based verification (ABV).
• Familiarity with industry‑standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.
• Experience with simulation and debug tools.
• Strong scripting skills in Python, Perl, or TCL for automation and data analysis.
• Excellent analytical, problem‑solving, and debugging skills.
• Strong communication skills and the ability to work effectively in a collaborative, cross‑functional team environment.

Job Information

Job Type: Regular
Shift: Shift 1 (India)
Primary Location: Regus, Madhapur
Additional Locations: Bengaluru, Karnataka, India

Equal Opportunity Employer Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.