FPGA Silicon Design Verification Engineer

844 Altera Semiconductor Technology India Pvt. Ltd.; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. is seeking an experienced FPGA Verification Engineer in Bengaluru, Karnataka. The role involves developing verification plans, executing simulations, and collaborating with design teams to ensure FPGA designs meet specifications.

The ideal candidate holds a Bachelor's Degree in Electrical Engineering, has at least 7 years of experience with SystemVerilog and UVM/OVM methodology, and is proficient in Perl or Python scripting. This is a regular position on Shift 1.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering.
• 7+ years of experience with SystemVerilog.
• 7+ years of experience with UVM or OVM methodology.
• 7+ years of experience scripting in Perl or Python.

Responsibilities

• Perform functional logic verification of FPGA.
• Develop verification plans and test benches.
• Execute verification plans and run simulations.
• Collaborate with architects and design teams.

Skills

SystemVerilog

UVM or OVM methodology

Scripting (Perl/Python)

Code coverage

Functional coverage

Ethernet protocols

Education

Bachelor's Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

Job description

Job Description

Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre‑silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate‑level‑simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Qualifications

Minimum Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum of 7 years of experience with SystemVerilog.
• Minimum of 7 years of experience with UVM or OVM methodology.
• Minimum of 7 years of experience with scripting Perl/Python.

Preferred Qualifications:

• Master’s Degree in Electrical Engineering, Computer Engineering, or related field.
• Experience with code coverage.
• Experience with functional coverage.
• Experience with X‑propagation.
• Experience with multiple RTL simulators.
• Experience with regression testing.
• Experience creating components that are reusable from block to top.
• Experience in Ethernet protocols.

Job Information

Job Type: Regular

Shift: Shift 1 (India)

Primary Location: Bengaluru, Karnataka, India

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.