Sr Principal Design Engineer

Cadence Design Systems, Inc.; Bengaluru; On-site; INR 5,000,000 - 7,000,000; Full time

Job summary

Cadence Design Systems, Inc. in India is seeking a senior DFT engineer to own the DFT scope across multiple projects in Bangalore/Pune. You will lead test architecture definitions and coordinate RTL changes for robust testability.

The role requires 10-15 years of experience in DFT/ASIC, experience with iJTAG, boundary scan, and high-speed/low-power designs. You will collaborate with customers, Marketing, and Pre-Sales to drive effective test solutions and post-silicon support.

Qualifications

• 10–15 years of DFT/ASIC experience.
• Experience with high-speed and low-power designs.
• Experience with DFT testability flows and post-silicon bring-up.

Responsibilities

• Own DFT across projects, including test architecture.
• Define test architecture and RTL changes for DFT.
• Perform scan insertion, LEC checks, and low power CLP checks.
• Develop timing constraints for test mode timing closure.
• Apply scan and ATPG for various fault models.
• Implement boundary scan, ACJTAG and IEEE 1500.
• IEEE1687 (iJTAG) compliant ICL/PDL for tests.
• Run zero delay and timing simulations and debug.
• Support post-silicon bring-up and field issues.
• Interact with customers and Marketing/Pre-Sales on DFT.
• Work on very high-speed and low-power designs.

Skills

DFT

ATPG

IEEE 1687

iJTAG

Boundary scan

Job description

PUNE 04

BANGALORE

Full time

R53296

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Experience: 10- 15 years

Location - Bangalore/Pune/

Responsibilities:

Complete DFT ownership of projects including:

• Test architecture definition.

• Identifying and implementing RTL changes for DFT.

• Performing scan insertion, LEC checks, low power CLP checks.

• Developing timing constraints for test mode timing closure.

• Scan and ATPG for different fault models.

• Boundary scan, ACJTAG, IEEE 1500 implementation and verification.

• IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.

• Running zero delay and timing simulations and debugging on all the above aspects.

• Supporting post silicon bring up.

• Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.

• Experience working on very high speed and low power designs.

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