Lead Design Engineer ( Synthesis/LEC/CLP )

Cadence Design Systems, Inc.; Bengaluru; On-site; INR 1,600,000 - 2,800,000; Full time

Job summary

Cadence Design Systems, Inc. in Bangalore is seeking a Lead Design Engineer to drive hands-on execution across Synthesis, LEC, CLP, and UPF/power‑intent flows for advanced ASIC/SoC designs.

You will debug synthesis issues, contribute to CLP sign‑off, and craft constraints and ECO scripts with a cross‑functional team. The role emphasizes independence, strong problem solving, and collaboration with PD, DFT, and RTL teams to deliver reliable closure.

Qualifications

• 5-8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows.
• Working knowledge of Cadence Genus and Conformal (LEC and/or CLP).
• Familiarity with UPF/CPF-based power intent (IEEE 1801).
• Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.
• Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts.
• Strong communication skills and ability to work independently on assigned blocks.

Responsibilities

• Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches
• Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues.
• Support CLP flows
• Write and maintain ECO scripts and timing/power constraints for design blocks
• Independently triage and document issues, escalating complex or systemic issues as needed.
• Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure
• Prepare clear status updates and technical summaries for internal tracking

Skills

ASIC synthesis

LEC

low-power verification

Cadence Genus

Conformal

UPF/CPF

Tcl scripting

Python scripting

Unix/Linux

STA basics

Power intent

Education

BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

Tools

Cadence Genus

Conformal

Job description

BANGALORE

PUNE

Full time

R56395

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success.

• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.

• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Experience: 5-8 Years

BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

Location: Bangalore/Ahmedabad/Pune

About the Role

We are looking for a Lead Design Engineer to provide hands‑on execution across Synthesis, LEC, CLP, and UPF/power‑intent flows for advanced ASIC/SoC designs. This role is execution‑focused with growing ownership: debugging synthesis and LEC issues independently, contributing to CLP sign‑off, and writing constraints and ECO scripts, while working closely with the Team on complex escalations.

Key Responsibilities

• Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches

• Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues.

• Support CLP flows

• Write and maintain ECO scripts and timing/power constraints for design blocks

• Independently triage and document issues, escalating complex or systemic issues as needed.

• Collaborate with PD, DFT, and RTL teams to resolve cross‑functional issues affecting synthesis/LEC/CLP closure

• Prepare clear status updates and technical summaries for internal tracking

Required Skills

• 5-8 years of hands‑on experience in ASIC synthesis, LEC, and/or low‑power verification flows

• Working knowledge of Cadence Genus and Conformal (LEC and/or CLP)

• Familiarity with UPF/CPF‑based power intent (IEEE 1801)

• Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments.

• Solid understanding of digital design fundamentals, STA basics, and low‑power architecture concepts

• Strong communication skills and ability to work independently on assigned blocks

Regards

K Madhu Prasad

[e-mail]

We’re doing work that matters. Help us solve what others can’t.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.