Sr. Memory Layout Design Engineer

Broadcom; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Broadcom in Bengaluru is seeking a seasoned Memory Layout Engineer with extensive experience in submicron CMOS processes. You will lead memory layout design, perform digital/analog layout considerations, and ensure quality, on-time deliverables in collaboration with SOC/library teams.

The role requires mentoring junior engineers, scripting for layout automation, and strong communication to adapt to evolving methodologies.

Qualifications

• Bachelor's degree in engineering or related field.
• 8+ years of experience in memory/layout design.
• Proficiency with Cadence layout tools and verification tools.

Responsibilities

• Understand and apply layout guidelines, process rules and requirements for high-quality layout.
• Manage scheduling, timelines, and layout floor-planning.

Skills

Memory layout design

Project leadership

Automation scripting

Team training

Education

Bachelor's degree

Tools

Cadence Virtuoso XL

Cadence VXL/EXL

Calibre

Job description

Broadcom · Ind-bangalore Electronic City - S1

Job Requirements

• Minimum 8 years of experience with strong layout knowledge
• Bachelor's degree required.
• Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).
• Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm)
• Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

Job Responsibilities

• Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout
• Manage scheduling, timelines, and layout floor-planning
• Responsible for start to end deliverables with quality within the planned schedule
• Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team
• Able to think and help in layout scripting and automation

Skill Set (Memory)

• Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes
• Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools
• Proficiency in floor-planning, hierarchy layout, and chip integration
• Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines
• Knowledge of AI, automation in layout, Script Programming and SKILL Programming
• Ability to lead, train junior engineers, and manage projects effectively
• Good knowledge of memory layout topology; experience with memory compilers is a plus
• Ability to lead new technology reviews to document layout methodologies, flows, and guidelines
• Self-reliant with the ability to work both independently and collaboratively

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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Avg wage $134K

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