Sr. Manager Physical Design Engineering

Advanced Micro Devices (AMD); Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Advanced Micro Devices (AMD) in Bengaluru seeks a senior leader to drive end-to-end Physical Design for complex SoC/ASIC programs, guiding floorplanning, PNR, timing and signoff while mentoring PD teams. You will lead full-chip and block-level PD execution, drive scalable methodologies, and collaborate with cross-functional groups to ensure high-quality silicon milestones.

This role requires deep expertise in PD disciplines, experience managing distributed teams, and a proven track record in

Qualifications

• Proven experience leading large-scale PNR teams and complex tapeouts.
• Deep expertise in Floorplanning, Place & Route, CTS, Timing Closure, Power Optimization, IR/EM Analysis, Physical Verification, and Signoff Methodologies.
• Strong executive communication and stakeholder management skills.
• Strong understanding of advanced technology nodes.
• Experience leading multi-site and geographically distributed teams.

Responsibilities

• Lead full-chip and block-level Physical Design execution.
• Drive Floorplanning, PNR, CTS, Timing Closure, Power Optimization, EMIR and Physical Verification signoff.
• Define and institutionalize scalable PD methodologies, flows, automation and best practices.
• Review technical quality, design readiness, milestone criteria, and signoff status.
• Drive technology enablement across new process nodes and advanced packaging technologies.
• Own PD schedules, deliverables, and milestone commitments.
• Track execution across multiple SoC programs and ensure tapeout readiness.
• Identify technical risks and drive mitigation plans.
• Partner with Program Management and Engineering leadership to resolve execution bottlenecks.
• Present program status, risks, recovery plans and resource needs to senior management.
• Build, mentor and retain a high-performing PD organization.
• Manage managers, technical leads, and senior engineers.
• Drive hiring strategy, succession planning, organizational scaling and capability development.
• Conduct performance reviews, career planning and growth discussions.
• Foster a culture of ownership, innovation, collaboration and engineering excellence.
• Partner with RTL, Architecture, DFT, FCT, DV, Power, Packaging, Silicon Validation and Product Engineering teams.
• Drive alignment across global engineering teams and external partners.
• Influence technical strategy and execution decisions across organizational boundaries.
• Define long-term PD roadmap and capability growth plans.
• Drive productivity improvements through automation, AI-enabled workflows and flow enhancements.
• Develop execution strategies for future products, process technologies and emerging methodologies.
• Represent the organization in engineering reviews and leadership forums.

Skills

PD leadership

Multi-site teams

Tapeout experience

Signoff methodologies

Job description

Job Summary

The Physical Design (PNR) Senior Manager is responsible for leading end-to-end Physical Design execution for complex SoC and ASIC programs, driving delivery from floorplanning through tapeout signoff. The role requires strong technical leadership in Place & Route, Timing Closure, Power, EMIR, Clocking, Physical Verification, and Design Methodology while managing multi-site engineering teams.

The successful candidate will build and lead high-performing physical design teams, drive execution excellence across multiple programs, develop organizational capability, and partner with cross-functional stakeholders to deliver best-in-class silicon products.

Responsibilities

Technical Leadership

• Lead full-chip and block-level Physical Design execution.
• Drive Floorplanning, PNR, CTS, Timing Closure, Power Optimization, EMIR and Physical Verification signoff.
• Define and institutionalize scalable PD methodologies, flows, automation and best practices.
• Review technical quality, design readiness, milestone criteria, and signoff status.
• Drive technology enablement across new process nodes and advanced packaging technologies.

Program Execution

• Own PD schedules, deliverables, and milestone commitments.
• Track execution across multiple SoC programs and ensure tapeout readiness.
• Identify technical risks and drive mitigation plans.
• Partner with Program Management and Engineering leadership to resolve execution bottlenecks.
• Present program status, risks, recovery plans and resource needs to senior management.

Organization & People Leadership

• Build, mentor and retain a high-performing PD organization.
• Manage managers, technical leads, and senior engineers.
• Drive hiring strategy, succession planning, organizational scaling and capability development.
• Conduct performance reviews, career planning and growth discussions.
• Foster a culture of ownership, innovation, collaboration and engineering excellence.

Cross-Functional Collaboration

• Partner with RTL, Architecture, DFT, FCT, DV, Power, Packaging, Silicon Validation and Product Engineering teams.
• Drive alignment across global engineering teams and external partners.
• Influence technical strategy and execution decisions across organizational boundaries.

Strategic Initiatives

• Define long-term PD roadmap and capability growth plans.
• Drive productivity improvements through automation, AI-enabled workflows and flow enhancements.
• Develop execution strategies for future products, process technologies and emerging methodologies.
• Represent the organization in engineering reviews and leadership forums.

Required Experience

• Proven experience leading large-scale PNR teams and complex tapeouts.
• Deep expertise in:
  • Floorplanning
  • Place & Route
  • CTS
  • Timing Closure
  • Power Optimization
  • IR/EM Analysis
  • Physical Verification
  • Signoff Methodologies
• Strong understanding of advanced technology nodes.
• Experience leading multi-site and geographically distributed teams.
• Demonstrated people-management experience including managing managers and technical leads.
• Strong executive communication and stakeholder management skills.

Preferred Qualifications

• Experience with AI, Datacenter, Automotive, GPU, CPU or High-Performance SoC products.
• Expertise in advanced packaging and/or 3DIC technologies.
• Experience driving methodology, automation, and flow-development initiatives.
• Strong understanding of cross-functional domains including DFT, FCT, Power, Architecture and Silicon Validation.
• #LI-BM2

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