Sr. Manager Physical Design Engineering

Advanced Micro Devices, Inc.; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Benefits offered by this job

AMD benefits

Job summary

Advanced Micro Devices, Inc. (AMD) seeks a Senior Manager of Physical Design (PNR) to lead end-to-end PD for complex SoC/ASIC programs, from floorplanning to tapeout.

You will drive Place & Route, Timing Closure, Power, EMIR, Clocking, Physical Verification and develop scalable PD methodologies while guiding multi-site teams. You will own PD schedules, mentor managers and engineers, hire and scale the organization, and partner with RTL, Architecture, DFT, Power, Packaging and Silicon Validation

Qualifications

• Must have proven experience leading large-scale PNR teams and complex tapeouts.
• Deep expertise in floorplanning, Place & Route, CTS and Timing Closure.
• Strong knowledge of Power Optimization, IR/EM, Physical Verification and signoff methodologies.

Responsibilities

• Lead full-chip and block-level Physical Design execution.
• Drive Floorplanning, PNR, CTS, Timing Closure, Power Optimization, EMIR and Physical Verification signoff.
• Define scalable PD methodologies, flows, automation and best practices.

Skills

Floorplanning

Place & Route

CTS

Timing Closure

Power Optimization

IR/EM Analysis

Physical Verification

Signoff Methodologies

multi-site leadership

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

Physical Design Lead (PNR)

THE ROLE

The Physical Design (PNR) Senior Manager is responsible for leading end-to-end Physical Design execution for complex SoC and ASIC programs, driving delivery from floorplanning through tapeout signoff. The role requires strong technical leadership in Place & Route, Timing Closure, Power, EMIR, Clocking, Physical Verification, and Design Methodology while managing multi-site engineering teams.

The successful candidate will build and lead high-performing physical design teams, drive execution excellence across multiple programs, develop organizational capability, and partner with cross-functional stakeholders to deliver best-in-class silicon products.

KEY RESPONSIBILITIES

Technical Leadership

• Lead full-chip and block-level Physical Design execution.
• Drive Floorplanning, PNR, CTS, Timing Closure, Power Optimization, EMIR and Physical Verification signoff.
• Define and institutionalize scalable PD methodologies, flows, automation and best practices.
• Review technical quality, design readiness, milestone criteria, and signoff status.
• Drive technology enablement across new process nodes and advanced packaging technologies.

Program Execution

• Own PD schedules, deliverables, and milestone commitments.
• Track execution across multiple SoC programs and ensure tapeout readiness.
• Identify technical risks and drive mitigation plans.
• Partner with Program Management and Engineering leadership to resolve execution bottlenecks.
• Present program status, risks, recovery plans and resource needs to senior management.

Organization & People Leadership

• Build, mentor and retain a high-performing PD organization.
• Manage managers, technical leads, and senior engineers.
• Drive hiring strategy, succession planning, organizational scaling and capability development.
• Conduct performance reviews, career planning and growth discussions.
• Foster a culture of ownership, innovation, collaboration and engineering excellence.

Cross-Functional Collaboration

• Partner with RTL, Architecture, DFT, FCT, DV, Power, Packaging, Silicon Validation and Product Engineering teams.
• Drive alignment across global engineering teams and external partners.
• Influence technical strategy and execution decisions across organizational boundaries.

Strategic Initiatives

• Define long-term PD roadmap and capability growth plans.
• Drive productivity improvements through automation, AI-enabled workflows and flow enhancements.
• Develop execution strategies for future products, process technologies and emerging methodologies.
• Represent the organization in engineering reviews and leadership forums.

REQUIRED EXPERIENCE

• Proven experience leading large-scale PNR teams and complex tapeouts.
• Deep expertise in:
  • Floorplanning
  • Place & Route
  • CTS
  • Timing Closure
  • Power Optimization
  • IR/EM Analysis
  • Physical Verification
  • Signoff Methodologies
• Strong understanding of advanced technology nodes.
• Experience leading multi-site and geographically distributed teams.
• Demonstrated people-management experience including managing managers and technical leads.
• Strong executive communication and stakeholder management skills.

PREFERRED QUALIFICATIONS

• Experience with AI, Datacenter, Automotive, GPU, CPU or High-Performance SoC products.
• Expertise in advanced packaging and/or 3DIC technologies.
• Experience driving methodology, automation, and flow-development initiatives.
• Strong understanding of cross-functional domains including DFT, FCT, Power, Architecture and Silicon Validation.
• #LI-BM2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.