Engineering Head

ACL Digital; Bengaluru; On-site; INR 6,000,000 - 9,500,000; Full time

Job summary

ACL Digital in Bengaluru seeks an executive technical leader to head the Physical Design (PD) engineering organization, steering 100+ PD engineers from synthesis, floorplanning, CTS, and routing to final timing, power, and sign-off on advanced nodes.

This role requires scale management, customer-facing executive leadership, and deep hands-on expertise to jump into technical blockages during high-stakes tape-outs.

Qualifications

• 18+ years in semiconductor implementation.
• Lead Physical Design organizations with 80–100 engineers.
• Direct ownership of multiple tape-outs on advanced nodes (7nm/5nm/3nm).

Responsibilities

• Lead, structure, and scale a 100+ PD engineering team across sites.
• Act as the technical escalation point for RTL-to-GDSII flows including P&R, CTS, and STA.
• Manage client relations, SLAs, and pre-silicon scoping with Tier-1 stakeholders.

Skills

PD leadership

RTL-to-GDSII

Synthesis

P&R

CTS

STA

EM/IR analysis

DRC/LVS

UPF/CPF

Scripting Tcl/Python

Automation

Client management

Education

B.Tech / M.Tech / M.S. in Electrical Engineering

VLSI

Microelectronics

Tools

Job description

Role Overview

We are seeking an executive technical leader to head our Physical Design (PD) engineering organization. Overseeing a team of 100+ PD engineers, you will drive execution from synthesis, floorplanning, CTS, and routing through to final timing, power, and physical sign-off on advanced nodes ( 5nm 3nm).

This role requires scale management, customer-facing executive leadership, and deep hands-on expertise to jump into technical blockages when high-stakes tape-outs encounter complex floorplanning, STA, or IR-drop challenges.

Key Responsibilities

1. Team & Resource Management (100+ Engineers)

• Lead, structure, and scale a 100+ engineer Physical Design unit, including Directors, Engineering Managers, and Principal PD Architects.
• Drive global headcount planning, project allocation, cross-site resource utilization, and skill development across implementation, timing, and physical verification tracks.

2. Hands-On Technical Authority & Execution

• Serve as the ultimate technical escalation point for RTL-to-GDSII implementation: Synthesis, Place & Route (P&R), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), EM/IR drop analysis, and DRC/LVS physical verification.
• Actively participate in architecture reviews, critical floorplan closures, low-power strategies (UPF/CPF), and high-frequency clock design for complex SOCs.
• Establish unified scripting (Tcl/Python), CAD flow automation, and compute-farm usage protocols to maximize throughput across all active projects.

3. Client Handling & Account Management

• Act as the senior executive escalation point for external semiconductor clients and Tier-1 stakeholders regarding physical design delivery, tape-out schedules, and technical risks.
• Partner with client leadership during pre-silicon scoping, statement-of-work (SOW) definitions, and technology node selection (foundry PDKs, IP integration, 2.5D/3D packaging).

Required Qualifications

• Education: B.Tech / M.Tech / M.S. in Electrical Engineering, VLSI, or Microelectronics.
• Experience: 18+ years in semiconductor implementation, with at least 4+ years leading Physical Design organizations of 80100+ engineers.
• Tape-out Proven: Direct ownership of multiple successful tape-outs on advanced nodes (7nm, 5nm, 3nm).
• Technical Depth: Ability to debug critical path closure, high-density placement bottlenecks, and complex sign-off violations directly with technical leads.
• Client Presence: Proven track record in customer-facing roles, managing SLAs, and running program steering committees.