Sr. DFT Engineer

NXP Semiconductors; Dadri; On-site; INR 900,000 - 1,300,000; Full time

Job summary

NXP Semiconductors in India (Dadri, Uttar Pradesh) is seeking an experienced DFT Engineer to design and validate DFT architectures for complex digital designs, with emphasis on scan, MBIST, and boundary scan, to ensure high test coverage and quality silicon.

You will collaborate with RTL, Physical Design, and STA teams, perform ATPG pattern generation, debug DFT issues, and support silicon bring-up and pattern validation.

Qualifications

• Strong expertise in scan, ATPG, and test methodologies for complex digital designs.
• Experience defining and implementing DFT architectures for high test coverage.
• Ability to debug DFT-related issues across design and silicon stages.

Responsibilities

• Define and implement DFT architecture including scan, MBIST, and boundary scan.
• Perform scan insertion, chain stitching, and compression techniques.
• Generate and analyze ATPG patterns to achieve high fault coverage.
• Debug and resolve DFT-related issues across design and silicon stages.
• Work closely with RTL, Physical Design, and STA teams for smooth integration.
• Support pattern validation, gate-level simulations, and silicon bring-up.
• Ensure compliance with DFT and testability requirements.

Skills

Scan

ATPG

DFT architectures

Test methodologies

Silicon bring-up

Job description

Design for Test (DFT) Engineer (Experienced) We are looking for an experienced DFT Engineer with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage and quality silicon.

Key Responsibilities

• Define and implement DFT architecture including scan, MBIST, and boundary scan.
• Perform scan insertion, chain stitching, and compression techniques.
• Generate and analyze ATPG patterns to achieve high fault coverage.
• Debug and resolve DFT-related issues across design and silicon stages.
• Work closely with RTL, Physical Design, and STA teams for smooth integration.
• Support pattern validation, gate-level simulations, and silicon bring-up.
• Ensure compliance with DFT and testability requirements.

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