Principle DFT Engineer

NXP Semiconductors; Bengaluru; On-site; INR 2,800,000 - 5,200,000; Full time

Job summary

NXP Semiconductors in Bengaluru seeks an experienced DFT Engineer (7–12 years) to design and verify scan architectures for complex SoCs. You will implement scan insertion, generate ATPG patterns, and analyze fault coverage for stuck-at and transition faults while performing GLS with and without SDF for DFT validation.

Collaborate closely with RTL, physical design, and test teams to ensure high fault coverage, clean DFT signoff, and timely tape-out support.

Qualifications

• 7–12 years of hands-on DFT engineering experience in complex SoC designs.
• Strong expertise in scan architectures, insertion, and GLS verification.
• Proficiency with industry DFT tools and RTL/physical collaboration.

Responsibilities

• Implement and verify scan architectures and scan insertion.
• Generate and analyze ATPG patterns for stuck-at and transition faults.
• Execute GLS with/without SDF for DFT validation and support tape-out.

Skills

Scan Insertion

ATPG

Gate-Level Simulation

GLS

Verilog

SystemVerilog

Tools

Tessent

Synopsys

Cadence

Job description

We are seeking an experienced DFT Engineer (7–12 years) with strong hands‑on expertise in Scan Insertion, ATPG, and Gate‑Level Simulation (GLS) for complex SoC designs. The candidate will be responsible for implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns for stuck‑at and transition faults, and executing GLS with and without SDF for DFT validation. The role requires close collaboration with RTL, physical design, and test teams to ensure high fault coverage, clean DFT signoff, and timely tape‑out support. Proficiency with industry‑standard DFT tools (Mentor/Siemens Tessent, Synopsys, or Cadence), solid Verilog/SystemVerilog skills, and the ability to debug DFT and GLS issues independently are essential. Prior experience supporting pre- and post‑silicon activities is a plus.

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