SoC Verification Engineer

SVTek; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

SVTek in Bengaluru is seeking a verification engineer with 2+ years of experience to verify complex digital designs using SystemVerilog and UVM. You will develop testbenches, write SVA, and drive coverage closure within an SoC design team.

The role requires hands‑on experience with VCS/Xcelium and scripting for test automation. Join a collaborative team that designs robust digital IP and integrates verification across platforms.

Qualifications

• Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering or related field.
• Minimum 2 years of hands‑on experience in digital design verification.
• Proficient in SystemVerilog, UVM, and writing SVA (SystemVerilog Assertions).
• Strong knowledge of functional coverage and code coverage methodologies.
• Hands‑on experience with industry-standard simulation tools like VCS and/or Xcelium.
• Solid understanding of RTL design (Verilog/VHDL), SoC architecture, and design debugging.
• Experience with scripting (Python, Perl, or Tcl) for test automation and regression.

Responsibilities

• Develop and execute verification plans for IP or SoC components.
• Build and maintain reusable testbenches using SystemVerilog and UVM methodology.
• Develop functional coverage and code coverage strategies to ensure design completeness.
• Write and debug SystemVerilog Assertions (SVA) for formal and dynamic verification.
• Design directed and constrained-random test cases.
• Perform coverage analysis and drive coverage closure.
• Collaborate with design teams to understand specifications and resolve bugs.
• Use simulation tools such as Synopsys VCS and Cadence Xcelium for verification tasks.

Skills

SystemVerilog

UVM

SystemVerilog Assertions

Functional coverage

Code coverage

Education

Bachelor's or Master’s degree in Electrical/Electronics/Computer Engineering

Tools

VCS

Xcelium

Cadence

Python scripting

Job description

About the Role

We are looking for a skilled and motivated Verification Engineer with 2+ years of experience to join our SoC Design team in Bangalore. You will be responsible for verifying complex digital designs using industry-standard methodologies and tools, ensuring robust and comprehensive verification coverage.

Key Responsibilities

• Develop and execute comprehensive verification plans for IP or SoC components.
• Build and maintain reusable testbenches using SystemVerilog and UVM methodology.
• Develop and implement functional coverage and code coverage strategies to ensure design completeness.
• Write and debug SystemVerilog Assertions (SVA) for formal and dynamic verification.
• Design directed and constrained-random test cases.
• Perform coverage analysis and drive coverage closure.
• Collaborate with design teams to understand specifications and resolve bugs.
• Use simulation tools such as Synopsys VCS and Cadence Xcelium for verification tasks.

Required Qualifications

• Bachelors or Master’s degree in Electrical/Electronics/Computer Engineering or related field.
• Minimum 2 years of hands‑on experience in digital design verification.
• Proficient in SystemVerilog, UVM, and writing SVA (SystemVerilog Assertions).
• Strong knowledge of functional coverage and code coverage methodologies.
• Hands‑on experience with industry-standard simulation tools like VCS and/or Xcelium.
• Solid understanding of RTL design (Verilog/VHDL), SoC architecture, and design debugging.
• Experience with scripting (Python, Perl, or Tcl) for test automation and regression.

To apply, please send your resume (PDF format) to [e-mail]