RTL Design Engineer, Sr Lead

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru is seeking an experienced RTL Design Engineer with 5+ years of front-end ASIC/SoC design expertise. You will lead micro-architecture development, RTL implementation, and signoff tasks including lint and CDC analyses to ensure silicon quality.

You will work closely with architecture, verification, DFT, and physical design teams to deliver high-quality silicon, develop SDC constraints, and support synthesis, timing analysis and tapeout readiness.

Qualifications

• 5+ years of experience in ASIC/SoC front-end design.
• Strong knowledge of digital design fundamentals.
• Hands-on RTL design with Verilog/SystemVerilog.
• Experience with lint and CDC tools and RTL quality checks.

Responsibilities

• Develop detailed micro-architecture specifications from high-level requirements.
• Design and implement synthesizable RTL using Verilog/SystemVerilog.
• Participate in design reviews and ensure quality and coding guideline compliance.
• Perform RTL quality checks (Lint, CDC/RDC, FSM and structural checks).
• Develop and maintain design documentation including micro-architecture interfaces.
• Collaborate with verification teams to define verification plans and resolve issues.
• Support synthesis, timing analysis, and timing closure activities.
• Develop and review SDC constraints for blocks and subsystems.
• Analyze/debug issues across simulation, synthesis, and implementation.
• Collaborate with DFT and physical design teams for tapeout readiness.

Skills

RTL design

Verilog/SystemVerilog

Lint/CDC analysis

Timing/SDC constraints

Education

Bachelor's/Master's in Electronics/EE/CS

PhD (related field)

Tools

SpyGlass

Questa Lint

SpyGlass CDC

Questa CDC

Design Compiler

Job description

Job Area

Engineering Group, Engineering Group > Hardware Engineering

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Job Description - 5+ year RTL designer
We are looking for a highly motivated RTL Design Engineer with 5+ years of experience in front-end ASIC/SoC design. The candidate will be responsible for micro-architecture development, RTL implementation, and quality signoff activities including Lint and CDC analysis. Experience with synthesis and timing constraints development is highly desirable. The role involves close collaboration with architecture, verification, DFT, and physical design teams to deliver high-quality silicon.

Key Responsibilities

• Develop detailed micro-architecture specifications from high-level architectural requirements.
• Design and implement synthesizable RTL using Verilog/SystemVerilog.
• Participate in design reviews and ensure design quality and compliance with coding guidelines.
• Perform RTL quality checks including:
  • Lint analysis and cleanup
  • CDC/RDC analysis and closure
  • FSM and structural checks
• Develop and maintain design documentation including micro-architecture and interface specifications.
• Work closely with verification teams to define verification plans and resolve functional issues.
• Support synthesis, timing analysis, and timing closure activities.
• Develop and review SDC constraints for block-level and subsystem-level designs.
• Analyze and debug issues across simulation, synthesis, and implementation stages.
• Collaborate with DFT and physical design teams for successful integration and tapeout.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC front-end design.
• Strong knowledge of digital design fundamentals.
• Hands-on expertise in:
  • RTL design using Verilog/SystemVerilog
  • Micro-architecture definition and documentation
  • Lint tools (SpyGlass, Questa Lint, or equivalent)
  • CDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent)
• Good understanding of clocking architectures, reset strategies, and low-power design concepts.
• Experience debugging RTL and simulation issues.

Preferred Qualifications

• Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.
• Experience creating and reviewing timing constraints (SDC).
• Understanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.
• Exposure to DFT methodologies and integration.
• Knowledge of low-power design techniques (UPF/CPF).
• Experience with complex SoC/IP development and integration.

Desired Skills

• Strong analytical and debugging skills.
• Excellent written and verbal communication.
• Ability to work independently and drive block ownership.
• Strong collaboration skills across architecture, verification, and physical design teams.

Nice to Have

• Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.
• Scripting knowledge in Python, Perl, or TCL for automation and flow enhancement.

Applicants

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