GPU (RTL) Design - Sr Engineer

MaC VC; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Qualcomm India Private Limited is seeking an experienced ASIC RTL Design Engineer in Bengaluru. You will work on complex RTL blocks, ensure timing closure, and collaborate with verification and validation teams for pre/post silicon debugging.

Proficiency in Verilog/SystemVerilog and AMBA protocols is required, with emphasis on multi-clock-domain designs and low power techniques. Minimum 3–4 years of relevant experience and a strong foundation in synthesis and timing concepts are essential.

Qualifications

• Minimum 3–4 years of ASIC RTL design experience.
• Proficient in Verilog/SystemVerilog RTL coding.
• Experience with multi-clock-domain blocks and asynchronous interfaces.
• Knowledge of AMBA protocols AXI/AHB/APB and clocking/reset/debug architecture.
• Synthesis using Design Compiler and timing concepts for ASICs; Primetime knowledge.
• Collaboration with design verification and pre/post silicon debug teams.
• Low power design experience is a plus.

Responsibilities

• Design and integrate complex RTL blocks for ASICs.
• Ensure timing closure and proper synthesis results.
• Work with verification teams for pre/post-silicon debugging.
• Apply low power techniques and manage multi-clock domains.

Skills

Verilog/SystemVerilog

AMBA AXI

AMBA AHB

AMBA APB

Multi-clock design

Low power design

Synthesis & timing

CDC & Lint

Education

Bachelor's degree in Electrical/Electronics or related

Master's degree in Electronics/CS or related

PhD in related field

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Minimum 3 to 4 years of work experience in ASIC RTL Design

Experience in Logic design/micro-architecture/RTL coding is a must.

Must have hands on experience with design and integration of complex multi clock domainblocks

Experience in Verilog/System-Verilog is a must.

Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Understanding of Memory controller designs and microprocessors is an added advantage

Work closely with the Design verification and validation teams for pre/post Silicon debug

Hands on experience in Low power design is preferable

Experience in Synthesis / Understanding of timing concepts for ASIC is must

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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