SOC Engineering Sr Staff Engineer STA

Synopsys Inc; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Synopsys Inc in Hyderabad, India seeks an experienced STA engineer to own block-level timing signoff and contribute to full-chip closure. You will drive constraints development, signoff across modes, and ECO validation while collaborating with PD, synthesis, and verification teams.

Strong scripting in TCL and Python is essential for automation. Ideal candidates have 8+ years in STA, with hands-on experience on PrimeTime and related tools, and exposure to low-power design considerations.

Qualifications

• 8+ years of experience in STA and timing closure
• Ownership of block-level STA signoff and full-chip timing closure
• Strong debugging skills for setup/hold, recovery/removal, clock gating

Responsibilities

• Own and execute block-level STA signoff and contribute to full-chip timing closure
• Develop and validate timing constraints (SDC) including clocks and IO constraints
• Run power signoff flows and analyze timing/power impacts of ECOs
• Assist in ECO generation and verify fixes through signoff checks
• Collaborate with synthesis/PD and verification teams to align constraints and parasitics
• Build automation in TCL/Python/Perl to improve STA productivity

Skills

STA engineering

Timing closure

Scripting TCL

Python

Perl

Education

BE/BTech or MTech in Electronics/Electrical Eng

Tools

PrimeTime

PrimePower/PT-PX

PrimeClosure/Tweaker

StarRC

Fusion Compiler/ICC2

Job description

Job Description:

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are

You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands‑on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full‑chip closure in collaboration with physical design, synthesis, and verification teams.

You have solid experience across the timing closure lifecycle—constraints development and validation, STA signoff, power analysis, and ECO support—and you enjoy solving complex timing issues under aggressive schedules. You communicate clearly, work effectively with global teams, and are motivated to improve productivity through scripting/automation (TCL/Python/Perl).

What You’ll Be Doing

• Own and execute block-level STA signoff and contribute to full‑chip timing closure for advanced process nodes.
• Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC‑related timing assumptions as applicable) and drive issue resolution with design/PD teams.
• Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
• Run and analyze power signoff/support flows (PrimePower / PT‑PX) and correlate timing/power impacts of ECOs.
• Support timing and power ECO generation, and validate fixes through signoff checks and regressions.
• Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).
• Use Synopsys tools such as PrimeTime, PrimePower/PT‑PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.
• Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.
• Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.

The Impact You Will Have

• Enable predictable and high‑quality timing closure for high‑performance, low‑power silicon.
• Improve first‑pass success through robust constraints, clean signoff, and disciplined closure practices.
• Strengthen team execution by contributing to repeatable STA flows, automation, and cross‑team alignment.
• Support successful project milestones through timely analysis, crisp communication, and ownership of deliverables.

What You’ll Need

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
• 8+ years of relevant experience in STA / timing closure (block ownership expected; full‑chip exposure preferred).
• Strong hands‑on experience in:
• Constraints development/validation (SDC)
• STA signoff across modes/corners, including MMMC concepts
• Timing closure debugging and ECO validation
• Power analysis/support (PrimePower / PT‑PX exposure preferred)
• Proficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT‑PX, PrimeClosure/Tweaker (preferred).
• Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
• Strong scripting skills in TCL (required) and Python/Perl (preferred).
• Understanding of low‑power and high‑frequency design considerations (UPF awareness is a plus).

Who You Are

Self‑driven, accountable, and comfortable working with minimal supervision on defined deliverables.

Strong analytical and debugging skills with attention to detail.

Clear communicator and effective collaborator across design, PD, and verification.

Open to learning, improving flows, and sharing knowledge within the team.

The Team You’ll Be A Part Of

You’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement—working closely with experts across domains to help customers achieve their silicon goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details on compensation and benefits during the hiring process.

Requirements: