Staff Engineer – Static Timing Analysis (STA)

TylSemi, Inc.; Karnataka; Hybrid; INR 3,200,000 - 5,200,000; Full time

Job summary

TYLsemi, Inc. in Bengaluru/Remote India is seeking an experienced Staff Engineer to lead Static Timing Analysis (STA) for complex SoCs and advanced-node designs.

You will drive timing closure across blocks and full-chip designs, collaborating with cross-functional teams and contributing to STA methodology improvements. The ideal candidate has 8+ years of STA/timing signoff experience, strong OCV/AOCV/POCV knowledge, and hands-on scripting in Tcl/Python.

Qualifications

• 8+ years of STA/timing signoff experience.
• Strong knowledge of OCV/AOCV/POCV and clocking methodologies.
• Hands-on scripting in Tcl, Python, or Perl for automation.

Responsibilities

• Lead block-level and full-chip STA activities including setup, hold, recovery, removal, and noise analysis.
• Drive timing closure across modes and corners using MMMC methodologies.
• Analyze timing violations with synthesis, CTS, P&R, and ECO teams.
• Define and validate timing constraints (SDC, exceptions, clocks).
• Perform timing signoff with industry STA tools; optimize ECOs.

Skills

STA expertise

Timing signoff

Clocking methodologies

Synthesis understanding

Scripting (Python/Tcl)

Education

Bachelor's or Master's in Electronics/Electrical/VLSI

Tools

Synopsys PrimeTime

CTS/Place-and-Route tools

Scripting for automation (Tcl/Python)

Job description

Staff Engineer – Static Timing Analysis (STA)

About this position

About TYLsemi, Inc.

The Opportunity

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.

No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team US team: Bay Area preferred, but we hire the best people regardless of location India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset.
• Bias for action.
• Deep technical expertise.
• Low ego, high standards.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are seeking an experiencedStaff Engineer – Static Timing Analysis (STA)to lead timing analysis and signoff activities for complex SoC and advanced-node designs. In this role, you will drive timing closure across multiple blocks and full-chip designs, collaborate with cross-functional implementation teams, and contribute to STAmethodologyimprovements. The ideal candidate shouldpossessstrongexpertisein timing signoff, MMMC analysis, and advanced timing optimization techniques.

What You’ll Do

• Lead block-level and full-chip STA activities including setup, hold, recovery, removal, and noise analysisDrive timing closure across multiple modes and corners using MMMC methodologiesAnalyze and debug complex timing violations in collaboration with synthesis, CTS, P&R, and ECO teamsDefine andvalidatetiming constraints including SDC generation, timing exceptions, and clock definitionsPerform timing signoff using industry-standard STA tools and methodologiesDrive ECO implementation and timing optimization with focus on performance, power, and area trade-offsContribute to automation,methodologyenhancement, and flow optimization initiatives

What We’re Looking For

• Bachelor’s orMaster’sdegree in Electronics, Electrical Engineering, or VLSI-related discipline8+ years of experience in STA, timing closure, or Physical Design signoff rolesStrong understanding of STA concepts including OCV/AOCV/POCV, SI/noise analysis, clocking methodologies, and timing exceptionsHands-on experience with SynopsysPrimeTimeand advanced timing signoff flowsGood understanding of synthesis, CTS, place-and-route, extraction, and ECO implementation flowsStrong scripting skills inTcl, Perl, Python, or Shell for automation and productivity improvement

Good to Have

• Experience with advanced-node technologies such as 7nm, 5nm, or belowExposure to low-power design methodologies including UPF/CPF and power-aware STAExperience in full-chip timing convergence and successfultapeoutexecution for large SoC designs

Success in This Role Looks Like

• Achieving timing closure with robust signoff quality across all operating modes and cornersEfficient resolution of complex timing issues with optimized performance, power, and area impactImproved STA productivity through automation andmethodologyenhancementsSuccessful collaboration across implementation and signoff teams leading totimelytapeoutexecution

Location

Hybrid / On-site - Bengaluru/ Remote - India