Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)

Source-Right; Bengaluru; On-site; INR 1,800,000 - 2,500,000; Full time

Job summary

Source-Right seeks a Senior Verification Engineer for DDR PHY verification from test planning through vector delivery, regression debugging, and final quality sign-off. You will tackle complex DDR PHY validation tasks and ensure protocol conformance with JEDEC standards.

Must-have expertise includes DDR PHY architecture, DFI, LPDDR5/LPDDR4, and advanced Verilog/SystemVerilog with UVM/OVM, plus strong debugging and root-cause skills for SS/SoC/post-silicon issues.

Qualifications

• DDR PHY architecture, DFI protocol, JEDEC standards (latest gens).
• LPDDR5/LPDDR4 hands-on experience.
• Verilog/SystemVerilog, UVM/OVM; strong debug and root-cause skills.

Responsibilities

• Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY.

Skills

DDR PHY architecture

DFI protocol

LPDDR5/LPDDR4

Verilog/SystemVerilog

UVM/OVM

Debug & root-cause

Tools

Perl scripting

AHB/AXI protocol knowledge

Job description

Position: Senior Verification Engineer, DDR PHY (IRT60ST RM 4494)

Verification ownership from testplan to vector delivery, regression debug, and quality sign-off for DDR PHY.

Must-have

• DDR PHY architecture, DFI protocol, JEDEC standards (latest gens)
• LPDDR5/LPDDR4 hands-on experience
• Verilog/SystemVerilog, UVM/OVM
• Strong debug and root-cause skills, including SS/SoC/post-silicon issues

Good To Have

• Perl scripting
• Post-silicon bring-up, HW-SW debug
• AHB/AXI protocol knowledge