Lead Design Verification DDR Engineer

Cadence; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Cadence in Bengaluru seeks a design and verification engineer with BE/BTech/ME/MTech in Electrical, Electronics or VLSI and 2+ years in Design Verification using SV/UVM.

The role emphasizes strong verification fundamentals, environment planning, test plan generation, and hands-on SystemVerilog coding to build verification environments and drive closure. Prior IP memory verification experience is a plus.

Qualifications

• BE/BTech/ME/MTech in Electrical/Electronics/VLSI.
• 2+ years of Design Verification experience with SV/UVM.
• Strong background in verification fundamentals, environment planning, and test plan generation.
• Experience in designing verification environments and leading projects from concept to verification closure.
• Hands-on SystemVerilog coding and UVM for verification environment development.
• Memory IP verification (DDR/HBM/GDDR) experience is a plus.

Responsibilities

• Verify complex designs and lead projects from concept to verification closure.
• Develop and maintain verification environments and test plans.
• Collaborate with IP teams and hardware teams to ensure verification coverage and closure.

Skills

SV/UVM

SystemVerilog coding

Verification fundamentals

Environment planning

Test plan generation

Environment development

IP verification

Education

BE/BTech/ME/MTech - Electrical / Electronics / VLSI

Job description

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
• 2+ years of Design Verification experience with SV/UVM
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• Design Verification experience verifying complex designs and leading projects from concept to verification closure.
• Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
• Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.