Lead Design Verification DDR Engineer

Cadence; Dadri; Vor Ort; INR 900.000 - 1.500.000; Vollzeit

Zusammenfassung

Cadence in India is seeking a Design Verification Engineer with BE/BTech/ME/MTech in Electrical/Electronics/VLSI and 2+ years SV/UVM experience to lead verification efforts.

The role emphasizes functional verification fundamentals, environment planning, test plan generation, and hands-on UVM/SystemVerilog coding to develop verification environments and verify complex designs, with memory IP verification as a plus.

Qualifikationen

• 2+ years of Design Verification experience with SV/UVM
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development
• Design Verification experience verifying complex designs and leading projects from concept to verification closure
• Strong hands-on UVM and System Verilog coding experience and functional verification environment development
• Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage

Jobbeschreibung

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
• 2+ years of Design Verification experience with SV/UVM
• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
• Design Verification experience verifying complex designs and leading projects from concept to verification closure.
• Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
• Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.