Senior Staff Engineer - DFT

Infineon Technologies AG; Bengaluru; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Infineon Technologies AG in Bengaluru seeks an experienced DFT architect to lead SoC DFT definition, implementation, verification, and silicon debug across complex SOCs.

You'll own JTAG/BSCAN/iJTAG, P1500, and push advances in scan, MBIST, and post-silicon debug while collaborating with cross-functional teams.

Qualifications

• 12+ years of experience in DFT implementation, verification, and post-silicon debug.

Responsibilities

• Define/implement/verify SoC DFT architecture and silicon debug.
• Implement Scan insertion, LPCT, LBIST, Hybrid-TK, and compression logic.
• Perform ATPG, DRC analysis, test coverage debug, memory BIST implementation/verification.
• Own JTAG/BSCAN/iJTAG, P1500 implementation/verification; fault models.
• Debug of ZERO-delay, SDF-based scan/MBIST/JTAG simulations.
• Analyze and debug test domains; post-silicon debug of scan/MBIST patterns.

Skills

DFT implementation

ATPG

Post-silicon debug

JTAG/BSCAN/iJTAG

P1500

Scan insertion

LPCT/LBIST

Scripting (Perl/Tcl/Python)

Testability analysis

Hardware verification

Education

Bachelor's degree in Electrical/Electronics

Master's degree in VLSI Design

Tools

LEC

CLP

Power analysis tools

Job description

Key responsibilities in your new role

• Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip
• Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures
• Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification
• Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck at/TDF/Bridging/Cell-aware/iddq fault models
• Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations
• Hands on experience in analysis and debug of above-mentioned test domains
• Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out

Your profile

• Bachelor's degree (B.E./B.Tech.) in Electrical/Electronics Engineering or Master's degree (M.E./M.Tech.) in VLSI Design or a related field
• 12+ years of experience in DFT implementation, verification, and post-silicon debug
• Strong understanding of the complete ASIC design flow
• Hands-on experience with LEC, CLP, and power analysis methodologies is highly desirable
• Proven expertise in delivering complex SOC designs, encompassing DFT specification development, implementation, verification, and post-silicon debug
• Self-driven professional with a passion for continuously improving DFT methodologies and design processes
• Excellent analytical and problem-solving abilities, with the capability to work independently, manage multiple priorities, and collaborate effectively within cross-functional teams
• Strong interpersonal and teamwork skills, with the ability to thrive in a diverse and dynamic work environment
• Proficiency in scripting languages such as Perl, Tcl, and Python is preferred

WeAreIn to leverage synergies contributing to Infineon’s product development. Are you in?

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion.

We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon.