Job DescriptionIn your new role you will:
- A degree in Electrical Engineering, Microelectronics or a similar field.
- At least 6 years of experience in Physical Design of highly complex SoCs.
- Experience in RTL coding, IP issues and handling is a plus.
- Programming skills and knowledge in scripting languages like Tcl, Perl or Python.
- Experience in working as a member of SoC design teams with high cost and quality awareness.
- Fluent English language skills - with German being an added plus.
- Understanding of industry standard tools for physical design and signoff.
- Be a quick learner and team player while taking and acting on responsibilities.
Your Profile
You are best equipped for this task if you have:
- Contributed to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design.
- Worked independently in different phases of the RTL2GDS flow with focus on Synthesis and Constraining for efficient Timing Closure, Equivalence check, PnR closure, IR/EM analysis and fixing along with physical checks cleanup sign-off.
- Worked with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow.
- Focused on PPA, defined the Partition shapes, pins and feedthrough along with IP integration guidelines are followed (reviewed along with IP owners) to suit the requirements.
- Analyzed and solved problems of high complexity using your global expert network.
- Drove the PnR closure of multimillion gate designs in lower technology nodes, performed SoC level IR/EM analysis, debugging and fixing.
- Ran SoC level Physical verification, debugging and fixing including Chip finishing, metal fill, Sealring and Tapeout checks.
- Be a member of an expert network and drive innovation, methodology for the RTL to GDS2 development cycle of next generation automotive SoCs.
Contact:
Gowri Shenoy, LinkedIn
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