Senior Silicon DFT Micro Architecture Engineer, Google Cloud

Google LLC; Bengaluru; On-site; INR 6,000,000 - 10,000,000; Full time

Job summary

Google LLC in Bengaluru is seeking a Share Senior Silicon DFT Micro Architecture Engineer for Google Cloud. This role focuses on leading DFT strategy and architecture across the ASIC development flow to deliver high-quality testability for Google's data-center hardware.

You will drive die-level validation, insert DFT IP blocks, and document test sequences while coordinating post-silicon support. The position involves in-person interviews and offers a chance to influence silicon bring-up, debug,

Qualifications

• Bachelor's degree as stated, or equivalent practical experience.
• 8 years of experience in the implementation and validation of DFT technologies.
• Experience with DFT design, verification, specification, architecture and insertion.
• Experience with ASIC DFT synthesis, simulation and verification flow.

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
• Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.
• Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Skills

DFT techniques

ASIC DFT synthesis

DFT verification flow

Leadership of DFT activities

Education

Bachelor's degree in Electrical Engineering or related field

Master's or PhD in Electrical/Computer Engineering or CS

Tools

DFT tools

Boundary scan

Test Access Point TAP

DFT IP integration

Job description

Share Senior Silicon DFT Micro Architecture Engineer, Google Cloud

In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 8 years of experience in the implementation and validation of DFT technologies.
• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
• Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
  
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
• Experience in fault modeling.
• Experience in SoC cycles, silicon bringup, and silicon debug activities.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design for Testing (DFT) micro-architect/design engineer, you will support the systems that are the heart of the world's largest and most powerful computing infrastructure. You will be part of a team that develops from the lowest levels of circuit design to large system design and sees those systems all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers, affecting millions of Google users.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
• Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.
• Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

• Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.