Senior DFT Design/Micro Architect Engineer, Google Cloud

Google; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Google is seeking a Design for Testing (DFT) specialist to shape testing strategies for cutting-edge TPU hardware. You will help verify complex digital designs, focusing on TPU architecture and its integration within AI/ML systems, across the full ASIC development lifecycle.

You will support from circuit-level to high-volume manufacturing and contribute to Google's data-center scale hardware. The role emphasizes innovation in DFT across AI/ML acceleration platforms.

Qualifications

• Bachelor's degree or equivalent practical experience in Electrical Engineering or related field.
• 8 years of experience implementing and validating DFT technologies.
• Experience with multiple DFT design and verification projects, DFT specification, architecture and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation and verification flow.
• Experience in leading DFT activities throughout an ASIC development flow.

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
• Drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and fix TDRC violations to achieve high test quality.
• Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Skills

DFT strategy

DFT architecture

die-level validation

TDRC

DFT IP blocks

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in Electrical/Computer Engineering or CS

Tools

DFT tools

ASIC DFT flow

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
• 8 years of experience in the implementation and validation of DFT technologies.
• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
• Experience in leading DFT activities throughout an ASIC development flow.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi die SoCs).
• Experience in fault modeling.
• Experience in SoC cycles, silicon bringup, and silicon debug activities.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Design for Testing (DFT) micro-architect/design engineer, you will support the systems that are the heart of the world's largest and most powerful computing infrastructure. The team develops from the lowest levels of circuit design to large system design and sees those systems all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers, affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high-speed I/Os, Analog DFT).
• Develop and drive die-level DFT validation strategy, complete all Test Design Rule Checks (TDRC), and execute design changes to fix TDRC violations to achieve high test quality.
• Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver production and debug patterns to the post-silicon engineering team, and run diagnosis for post-silicon support.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .