Senior RTL Design Engineer

LeadSoc Technologies Pvt Ltd; Hyderabad; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd seeks a Senior RTL Design Engineer in Hyderabad to develop and integrate synthesizable RTL for complex Ethernet-based SoC/IP designs. The role demands hands-on RTL coding, strong microarchitecture skills, and close collaboration with Architecture, DV, STA and Physical Design teams.

Responsibilities include translating specifications into RTL, performing lint/CDC checks, debugging issues, and driving RTL optimization for PPA, timing, area and power.

Qualifications

• Strong hands-on experience with RTL design in Verilog/SystemVerilog.
• Solid understanding of microarchitecture from specifications.
• Experience with Ethernet protocols/IP and high-speed networking.

Responsibilities

• Develop and integrate synthesizable RTL for complex SoC/IP designs.
• Translate microarchitecture specs into efficient RTL.
• Perform lint, CDC/RDC and RTL quality checks using SpyGlass.
• Debug RTL, CDC, lint and functional issues.
• Collaborate with Architecture, DV, STA and Physical Design teams.
• Drive RTL optimization for PPA, timing, area and power.

Skills

Verilog/SystemVerilog RTL

Microarchitecture understanding

Ethernet knowledge (MAC/PCS/PHY)

CDC, clocking, reset concepts

RTL coding practices

Tools

SpyGlass Lint

SpyGlass CDC

Job description

Senior RTL Design Engineer

Location:

Hyderabad

Experience:

3–6 Years

Role Overview

We are looking for a Senior RTL Design Engineer with strong hands-on expertise in Ethernet-based SoC/IP design, RTL development, and design quality checks.

Key Responsibilities

• Develop and integrate synthesizable RTL for complex SoC/IP designs.
• Strong hands-on experience with Ethernet protocols/IP and high-speed networking designs.
• Translate microarchitecture specifications into efficient RTL.
• Perform Lint, CDC/RDC and RTL quality checks using SpyGlass.
• Debug and resolve RTL, CDC, lint and functional issues.
• Collaborate with Architecture, DV, STA and Physical Design teams.
• Drive RTL optimization for PPA, timing, area and power.

Core Technical Skills

• Strong Verilog/SystemVerilog RTL design experience.
• Solid microarchitecture understanding and ability to work from specifications.
• Strong Ethernet knowledge — MAC/PCS/PHY, 10G/25G/100G/400G exposure preferred.
• Hands-on experience with SpyGlass Lint & CDC.
• Strong understanding of CDC, reset architecture, clocking and RTL coding practices.
• Experience with synthesis, timing and PPA optimization.
• Strong debugging and problem-solving skills.

Ideal Candidate:

A hands-on RTL engineer with strong Ethernet + Microarchitecture + Lint/CDC + SpyGlass expertise and experience delivering production-quality SoC/IP designs.