Senior RTL Design Engineer

HCLTech; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Benefits offered by this job

Health insurance

Career growth opportunities

Job summary

HCL Technologies Limited seeks experienced SoC Verification and Emulation Engineers to support server platform verification efforts. You will develop verification plans, debug complex issues, and drive verification closure in pre-silicon and emulation environments.

Candidate should have strong SystemVerilog/UVM verification, Python automation, and experience validating infrastructure features including Reset, Security, RAS, Clocking, Power, GPIO, Debug, and Fuse flows.

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, CS, or related field.
• 3 to 12 years of experience in SoC Verification, Pre‑Silicon Validation and Emulation.
• 経験 in SoC verification and emulation environments is preferred.

Responsibilities

• Develop verification plans and execute verification activities for SoC platforms.
• Debug complex SoC issues and drive verification closure in pre-silicon and emulation.
• Verify Debug Fabrics including VISA, Trace, Observability, Trigger, TAP/JTAG validation.
• Validate SoC Platform Infrastructure: Reset, Security, RAS, Fuse, GPIO, Clocking, Power.
• Create and maintain verification environments, checkers, scoreboards and regression tests.
• Automate test execution with Python and maintain test benches.
• Analyze waveform, triage failures and perform root-cause analysis.
• Collaborate with architecture, design and firmware teams to resolve issues.
• Apply Intel Xeon/Client verification methodologies and validation flows.

Skills

SystemVerilog/UVM

Python scripting

Functional verification

Testbench development

Debug and validation

Education

Electronics/EE/CS degree

Tools

TAP/JTAG

Job description

We are seeking experienced SoC Verification and Emulation Engineers to support server platform verification activities. The candidate will be responsible for developing and executing verification plans, debugging complex SoC issues, and driving verification closure in pre-silicon and emulation environments.

The role requires strong expertise in SystemVerilog/UVM-based verification methodologies, Python-based automation, and functional validation of critical infrastructure features including Security, Reset, RAS, Clocking, Power Management, GPIO, Debug and Fuse flows.

Key Responsibilities

• Strong expertise in SoC Pre‑Silicon Verification and Emulation using SystemVerilog, UVM, Assertions (SVA), Functional Coverage, and Testbench Development.
• Hands‑on experience in developing verification environments, checkers, scoreboards, test cases, and regression execution frameworks.
• Proven experience in verifying Debug Fabrics, including VISA, Trace, Observability, Trigger, and TAP/JTAG-based validation.
• Experience in validating SoC Platform Infrastructure and System Control Flows, including Reset, Security, RAS, Fuse, GPIO, Clocking, and Power Management.
• Strong proficiency in Python scripting and automation for pre‑silicon and emulation‑based test execution.
• Hands‑on experience with SoC emulation platforms, including test execution, debug, regression management, and coverage closure.
• Expertise in verification debug tools, waveform analysis, failure triage, and root‑cause analysis of complex SoC issues.
• Ability to analyze and resolve SoC integration and functional validation issues in collaboration with architecture, design, and firmware teams.
• Good understanding of Intel Xeon/Client verification methodologies and validation flows.

Strong analytical, communication, and problem-solving skills with the ability to work effectively in cross‑functional global teams.

Skill Requirements

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Other Requirements

• 3 to 12 years of experience in SoC Verification, Pre‑Silicon Validation and Emulation.