Technical Architect - RTL Design

HCLTech; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

HCL Technologies Limited in Bangalore is seeking an experienced SoC Verification and Emulation Engineer focused on pre-silicon validation, debugging, and global flow optimization. The candidate will drive verification closure using SystemVerilog/UVM, Python automation, and robust testing strategies.

The role requires hands-on verification environment development, coverage analysis, and strong collaboration with architecture, design, and firmware teams to ensure successful validation of security,

Qualifications

• Strong expertise in SystemVerilog/UVM-based verification methods (SVA, coverage, testbench development).
• Hands-on experience with pre-silicon verification and emulation environments.
• Proven ability to debug complex SoC issues and drive verification closure.

Responsibilities

• Develop and execute verification plans for SoC verification.
• Debug and triage complex SoC issues across pre-silicon and emulation flows.
• Validate platform infrastructure, security, reset, RAS, clocking, and power management features.
• Create verification environments, checkers, scoreboards, and regression frameworks.
• Collaborate with architecture, design, and firmware teams across global sites.

Skills

SystemVerilog/UVM

Python

Verification

Debugging

Education

Bachelor's or Master's in Electronics/EE/CS

Tools

Emulation platforms

Job description

Career Opportunities: Technical Architect - RTL Design (162264)

Requisition ID162264-Posted11/10/2026

JD1 : SoC Pre-Silicon Verification & Emulation Engineer (Debug Fabrics and Global Flows)Location:Bangalore
Number of Positions: 10-14Job SummaryWe are seeking experienced SoC Verification and Emulation Engineers to support server platform verification activities. The candidate will be responsible for developing and executing verification plans, debugging complex SoC issues, and driving verification closure in pre-silicon and emulation environments.The role requires strong expertise in SystemVerilog/UVM-based verification methodologies, Python-based automation, and functional validation of critical infrastructure features including Security, Reset, RAS, Clocking, Power Management, GPIO, Debug and Fuse flows.

Key Responsibilities

Strong expertise in SoC Pre-Silicon Verification and Emulation using SystemVerilog, UVM, Assertions (SVA), Functional Coverage, and Testbench Development.Hands-on experience in developing verification environments, checkers, scoreboards, test cases, and regression execution frameworks.Proven experience in verifying Debug Fabrics, including VISA, Trace, Observability, Trigger, and TAP/JTAG-based validation.Experience in validating SoC Platform Infrastructure and System Control Flows, including Reset, Security, RAS, Fuse, GPIO, Clocking, and Power Management.Strong proficiency in Python scripting and automation for pre-silicon and emulation-based test execution.Hands-on experience with SoC emulation platforms, including test execution, debug, regression management, and coverage closure.Expertise in verification debug tools, waveform analysis, failure triage, and root-cause analysis of complex SoC issues.Ability to analyze and resolve SoC integration and functional validation issues in collaboration with architecture, design, and firmware teams.Good understanding of Intel Xeon/Client verification methodologies and validation flows.Strong analytical, communication, and problem-solving skills with the ability to work effectively in cross‑functional global teams.

Skill Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, Computer Science, or a related field.3 to 12 years of experience in SoC Verification, Pre‑Silicon Validation and Emulation.

Other Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, Computer Science, or a related field.3 to 12 years of experience in SoC Verification, Pre‑Silicon Validation and Emulation.