Senior IP Verification Engineer

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is seeking a Senior Design Verification Engineer with 8–10 years of experience to verify FPGA/ASIC IPs in a Hyderabad setting.

The role focuses on front-end verification, collaborating across architecture, IP design, PD and product engineering to drive first-pass silicon success. You will develop test plans, build UVM-based testbenches, and run comprehensive regressions while mentoring junior team members.

Qualifications

• Experience with PCIe, CXL or Ethernet protocols is preferred.
• Expert in IP level ASIC verification and verification environments.
• Proficient in Verilog and SystemVerilog, OO programming, and UVM-based testbenches.

Responsibilities

• Collaborate with architects, hardware and firmware engineers to understand new features to be verified for PCIe/CXL based IPs.
• Develop test plan documentation considering interactions with features, hardware, firmware and software drivers.
• Code IP or SS level UVM-based testbenches, verification components - monitors, scoreboard, checkers.
• Build directed and random verification tests.
• Run regressions and debug test failures to ensure high design quality.

Skills

PCIe verification

CXL verification

Ethernet protocols

Verilog

SystemVerilog

UVM framework

Testbench development

Scripting/automation

Python/Perl

Education

Bachelors or Masters in Computer Engineering/Electrical Engineering

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Senior Design Verification Engineer
Experience: 8-10 Years

Location: Hyderabad

Full Time Employment/Contratual

Role & responsibilities

Job Title: Verification Engineer

Experience: 8-10 Years

THE ROLE:

As an IP verification engineer you will help bring to life cutting-edge FPGA, ASICs for variety of target customers.As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.

KEY RESPONSIBLITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
• Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
• Build the directed and random verification tests
• Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

PREFERRED EXPERIENCE:

• Experience with PCIe or CXL or ethernet protocols is preferred
• Proficient in IP level ASIC verification
• Expert in Verilog, System Verilog, Object Oriented programming
• Expertise in developing UVM based verification frameworks and testbenches
• Scripting and automation of verification processes and flows
• Exposure to leadership or mentorship is an asset
• Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Comfortable in python / perl and editing / maintaining scripts
• Strong communication skills and the ability to work independently as well as in a cross-site team environment
• Good Computer Architecture, systems knowledge is a plus
• Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering