Senior Design Verification Lead

NXP acquires Kinara, Inc.; Hyderabad; On-site; INR 2,400,000 - 3,600,000; Full time

Job summary

NXP acquires Kinara, Inc. is seeking a Senior ASIC Hardware Verification Engineer in Hyderabad to architect advanced UVM testbenches and lead coverage closure for complex digital designs. The role emphasizes end-to-end verification of IP, Subsystems, or SoCs and collaboration with RTL teams.

You will define verification plans, implement scalable environments, and mentor junior engineers while ensuring design correctness before tape-out. Strong SystemVerilog and debugging skills are essential.

Qualifications

• 7+ years of experience in ASIC/SoC verification.
• Expertise in UVM-based testbenches and SystemVerilog.
• Strong debug and coverage-closure skills.

Responsibilities

• Verification Strategy: Define and document the verification plan (vPlan), including test scenarios, checkers, and functional coverage models.
• Testbench Architecture: Architect reusable verification environments using SystemVerilog and UVM.
• Advanced Stimulus: Develop constrained-random stimulus and directed tests to stress-test corner cases.
• Debugging: Root-cause hardware failures by analyzing waveforms and collaborating with RTL designers.
• Coverage Closure: Drive functional and code coverage to 100% with refined stimulus.
• Performance & Power: Verify throughput, latency, and UPF/CPF-based power features.
• Mixed-Methods: Integrate Formal Verification and Hardware Emulation for long-latency tests.
• Mentorship: Provide technical leadership and perform code reviews.

Skills

UVM

SystemVerilog

Verification planning

Debugging waveforms

Tools

JasperGold

VC Formal

Palladium/Zebu

Job description

The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC). You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the "coverage closure" process to ensure the design meets all architectural specifications before tape-out.

Job Location : Hyderabad

Experience Level 7+years

The Senior ASIC Hardware Verification Engineer is responsible for the end-to-end functional verification of complex digital designs (IP, Subsystem, or SoC). You will architect advanced UVM-based testbenches, define exhaustive verification plans, and lead the "coverage closure" process to ensure the design meets all architectural specifications before tape-out.

Key Responsibilities

• Verification Strategy: Define and document the verification plan (vPlan), including test scenarios, checkers, and functional coverage models.
• Testbench Architecture: Architect and implement scalable, reusable verification environments using SystemVerilog and UVM.
• Advanced Stimulus: Develop constrained-random stimulus and directed tests to stress-test corner cases of the micro-architecture.
• Debugging: Root-cause complex hardware failures by analyzing waveforms (VPD/FSDB) and collaborating with RTL designers.
• Coverage Closure: Drive functional and code coverage to 100%, utilizing exclusions and refined stimulus to reach uncovered logic.
• Performance & Power: Verify throughput, latency, and power-aware (UPF/CPF) features of the silicon.
• Mixed-Methods: Integrate Formal Verification (JasperGold/VC Formal) for control logic and Hardware Emulation (Palladium/Zebu) for long-latency system tests.
• Mentorship: Provide technical leadership to junior engineers and perform code reviews for testbench components.