Senior Director - DFT

Altera; Bengaluru; On-site; INR 5,000,000 - 9,000,000; Full time

Benefits offered by this job

Health insurance

Job summary

Altera seeks an experienced DFT Technical Leader to drive advanced DFT methodologies across FPGA products. You will be the technical authority for DFT architecture, methodology, and implementation while building and leading the DFT engineering team.

You will work across design, silicon, and manufacturing to improve test readiness and yield. You will define DFT strategies for subsystems, mentor engineers, and partner with RTL, physical design, and validation teams.

Qualifications

• 15+ years in semiconductor engineering including 12+ years in DFT development, implementation, and deployment (13+ with MS, 10+ with PhD).
• Deep hands-on expertise in DFT architecture and implementation, including scan and test compression, ATPG, MBIST/BISR, JTAG/boundary scan, and silicon bring-up/debug.
• Proficiency in scripting for DFT flow (Python, TCL, and/or Perl).

Responsibilities

• Define and drive DFT architecture, methodology, and implementation strategy for next-generation FPGA products from specification through tapeout, silicon bring-up, and production.
• Serve as the technical authority for DFT across the organization, guiding complex decisions and mentoring engineers on advanced DFT concepts.
• Define DFT strategies across FPGA subsystems including programmable logic, memories, and high-speed I/O.
• Define hierarchical/multi-die DFT architectures for chiplet-based and 2.5D/3D-packaged products.
• Partner with RTL, physical design, verification, silicon validation, and test teams to embed DFT requirements across the lifecycle.
• Drive improvements in test readiness, coverage, fault detection, efficiency, and yield via DFT tooling and automation.
• Lead cross-organizational resolution of post-silicon DFT issues including test-pattern bring-up and yield improvement.
• Identify emerging DFT technologies and influence roadmaps and engineering processes.
• Build and develop a DFT team, manage resources, and oversee tool/vendor strategy.
• Define and track DFT metrics and present strategy to senior leadership.

Skills

DFT architecture

ATPG

MBIST/BISR

JTAG/boundary scan

DFT verification

silicon bring-up/debug

Python/TCL/Perl scripting

team leadership

cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field

MS degree in a related field

PhD in a related field

Tools

Tessent

Modus

Advantest V93000

Teradyne UltraFLEX

IEEE 1149.1 boundary scan

IEEE 1687 (IJTAG)

IEEE 1838

Job description

Job Description

Altera is seeking an experienced DFT Technical Leader to drive advanced Design-for-Test (DFT) methodologies across next-generation FPGA products. You will be the technical authority for DFT architecture, methodology, and implementation while building and leading the DFT engineering team.

Job Details

Job Description

Altera is seeking an experienced DFT Technical Leader to drive advanced Design-for-Test (DFT) methodologies across next-generation FPGA products. You will be the technical authority for DFT architecture, methodology, and implementation while building and leading the DFT engineering team.

You will work across the design, silicon, and manufacturing organizations to improve test readiness, accelerate bring-up, and drive measurable yield improvement.

Responsibilities

• Define and drive DFT architecture, methodology, and implementation strategy for next-generation FPGA products from specification through tapeout, silicon bring-up, and production, with methodologies that scale across product generations and design teams.
• Serve as the technical authority and subject matter expert for DFT across the organization, guiding complex technical decisions and mentoring engineers on advanced DFT concepts, methodologies, and implementation challenges.
• Define DFT strategies across key FPGA subsystems, including programmable logic, embedded memories, hardened IP, configuration infrastructure, and high-speed I/O.
• Define hierarchical and multi-die DFT architectures for chiplet-based and 2.5D/3D-packaged products, including die-to-die interface test, streaming scan network approaches, and known-good-die strategy.
• Partner closely with RTL and physical design, verification, silicon validation, product engineering, manufacturing, and test teams to ensure DFT requirements are incorporated throughout the product development lifecycle.
• Drive improvements in test readiness, test coverage, fault detection, test efficiency, and overall testability, and reduce silicon-to-product bring-up time through DFT architecture, automation, and debug capability.
• Lead technical resolution of complex, cross-organizational DFT issues post-silicon: test-pattern bring-up, failure diagnosis, correlation, and yield improvement.
• Identify emerging DFT technologies, standards, and industry trends, and influence technical roadmaps, architecture decisions, and engineering processes accordingly.
• Build, lead, and develop a team of DFT engineers (hiring, technical coaching, performance management, and career development), and own DFT resource planning, execution commitments across concurrent programs, and EDA tool and vendor strategy.
• Define and track key DFT metrics (test coverage, test-to-product bring-up time, test efficiency, and yield), and represent DFT technical strategy and recommendations to senior engineering leadership.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, with 15+ years in semiconductor engineering including 12+ years of hands-on DFT development, implementation, and deployment (13+ years with an MS, 10+ years with a PhD).
• Deep hands-on expertise in DFT architecture and implementation, including scan and test compression, ATPG, MBIST/BISR, JTAG/boundary scan, DFT verification, and silicon bring-up/debug, on complex ASIC, SoC, or FPGA products.
• Demonstrated expertise with industry-standard DFT tooling and standards, including commercial ATPG and DFT insertion tools (e.g., Tessent, Modus), IEEE 1149.1 boundary scan, IEEE 1687 (IJTAG), and IEEE 1838, plus a track record of adopting or advancing new DFT technologies.
• Demonstrated improvement of silicon bring-up, test readiness, test coverage, manufacturing test, or product yield through DFT.
• Proficiency in scripting and automation (Python, TCL, and/or Perl) for DFT flow, tool, and methodology development.
• Experience leading engineers as a manager or team lead (hiring, technical mentoring, and performance development), and influencing architecture, methodology, and technical direction across multiple engineering teams.
• Strong understanding of semiconductor manufacturing, test, yield, and product development processes, with excellent cross-functional communication skills.

Preferred Qualifications

• Experience with FPGA-specific DFT challenges in high-volume manufacturing, including programmable fabric, configuration memory, and SerDes.
• Experience reducing test time and cost of test on production ATE platforms (e.g., Advantest V93000, Teradyne UltraFLEX) and driving DPPM and test-quality targets.
• Experience with advanced process technologies, multiple product generations, and increasingly complex SoC/FPGA architectures.
• External recognition as a DFT expert: patents, publications, conference presentations (e.g., ITC, VTS), or participation in industry standards bodies or working groups.

Job Type

Regular

Shift

Shift 1 (India)

Primary Location

Bengaluru, Karnataka, India

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.