Senior DFT Engineer

Veedee Solutions LLP; Mumbai; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Veedee Solutions LLP in Mumbai, India is seeking a Senior DFT Engineer to lead DFT strategies for complex SOC designs. You will work with design and verification teams to ensure high fault coverage and robust testability, using advanced DFT techniques and industry tools.

The role requires deep experience in scan insertion, MBIST/ATPG, and SOC signoff processes. You will mentor junior engineers and collaborate across cross-functional teams to maintain project timelines and quality.

Qualifications

• Extensive experience in DFT architectures and methodologies.
• Managing scan insertion, test pattern validation, and fault coverage analysis.
• Familiar with SOC design flows and signoff processes.

Responsibilities

• Develop and implement DFT architectures for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis.
• Utilize Tessent for MBIST and ATPG to improve coverage and efficiency.
• Collaborate with design teams to integrate DFT features into flow and standards.
• Conduct DFT DRC checks and resolve issues during design.
• Provide guidance and mentorship on DFT practices.

Skills

DFT techniques

MBIST/ATPG

Fault coverage analysis

SOC design & signoff

Problem-solving

Communication & teamwork

Tools

Tessent

Job description

We are seeking a highly skilled Senior DFT Engineer to join our dynamic team. The ideal candidate will have extensive experience in design for testability (DFT) methodologies and will be responsible for ensuring the highest levels of fault coverage and testability in our semiconductor products. As a Senior DFT Engineer, you will work closely with design and verification teams to implement DFT strategies that meet project requirements and timelines.

Key Responsibilities:

• Develop and implement DFT architectures and methodologies for complex SOC designs.
• Perform scan insertion, test pattern validation, and fault coverage analysis to ensure robust testability.
• Utilize tools such as Tessent for MBIST and ATPG to enhance test coverage and efficiency.
• Collaborate with cross-functional teams to integrate DFT features into the design flow and ensure compliance with industry standards.
• Conduct DFT DRC checks and resolve any issues that arise during the design process.
• Provide technical guidance and mentorship to junior engineers in DFT practices and methodologies.

Required Skills:

• Strong knowledge of DFT techniques including scan insertion, MBIST, and ATPG.
• Proficiency in using DFT tools such as Tessent.
• Experience with fault coverage analysis and test pattern validation.
• Familiarity with SOC design and signoff processes.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork abilities.

If you are passionate about DFT and looking to make a significant impact in a fast-paced environment, we encourage you to apply for this exciting opportunity.